UefiCpuPkg/SmmCpuFeaturesLibStm: Add STM library instance

[mirror_edk2.git] / UefiCpuPkg / Library / SmmCpuFeaturesLib / X64 / SmmStmSupport.c

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c
new file mode 100644 (file)
index 0000000..6681234
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c
@@ -0,0 +1,95 @@
+/** @file\r
+  SMM STM support functions\r
+\r
+  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiSmm.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#include "SmmStm.h"\r
+\r
+///\r
+/// Page Table Entry\r
+///\r
+#define IA32_PG_P                   BIT0\r
+#define IA32_PG_RW                  BIT1\r
+#define IA32_PG_PS                  BIT7\r
+\r
+/**\r
+\r
+  Create 4G page table for STM.\r
+  2M PAE page table in X64 version.\r
+\r
+  @param PageTableBase        The page table base in MSEG\r
+\r
+**/\r
+VOID\r
+StmGen4GPageTable (\r
+  IN UINTN              PageTableBase\r
+  )\r
+{\r
+  UINTN                             Index;\r
+  UINTN                             SubIndex;\r
+  UINT64                            *Pde;\r
+  UINT64                            *Pte;\r
+  UINT64                            *Pml4;\r
+\r
+  Pml4 = (UINT64*)(UINTN)PageTableBase;\r
+  PageTableBase += SIZE_4KB;\r
+  *Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P;\r
+\r
+  Pde = (UINT64*)(UINTN)PageTableBase;\r
+  PageTableBase += SIZE_4KB;\r
+  Pte = (UINT64 *)(UINTN)PageTableBase;\r
+\r
+  for (Index = 0; Index < 4; Index++) {\r
+    *Pde = PageTableBase | IA32_PG_RW | IA32_PG_P;\r
+    Pde++;\r
+    PageTableBase += SIZE_4KB;\r
+\r
+    for (SubIndex = 0; SubIndex < SIZE_4KB / sizeof (*Pte); SubIndex++) {\r
+      *Pte = (((Index << 9) + SubIndex) << 21) | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;\r
+      Pte++;\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  This is SMM exception handle.\r
+  Consumed by STM when exception happen.\r
+\r
+  @param Context  STM protection exception stack frame\r
+\r
+  @return the EBX value for STM reference.\r
+          EBX = 0: resume SMM guest using register state found on exception stack.\r
+          EBX = 1 to 0x0F: EBX contains a BIOS error code which the STM must record in the\r
+                           TXT.ERRORCODE register and subsequently reset the system via\r
+                           TXT.CMD.SYS_RESET. The value of the TXT.ERRORCODE register is calculated as\r
+                           follows: TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC\r
+          EBX = 0x10 to 0xFFFFFFFF - reserved, do not use.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+SmmStmExceptionHandler (\r
+  IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context\r
+  )\r
+{\r
+  // TBD - SmmStmExceptionHandler, record information\r
+  DEBUG ((DEBUG_ERROR, "SmmStmExceptionHandler ...\n"));\r
+  //\r
+  // Skip this instruction and continue;\r
+  //\r
+  Context.X64StackFrame->Rip += Context.X64StackFrame->VmcsExitInstructionLength;\r
+\r
+  return 0;\r
+}\r