;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
.model flat,C\r
.xmm\r
\r
+MSR_IA32_MISC_ENABLE EQU 1A0h\r
+MSR_EFER EQU 0c0000080h\r
+MSR_EFER_XD EQU 0800h\r
+\r
+;\r
+; Constants relating to PROCESSOR_SMM_DESCRIPTOR\r
+;\r
DSC_OFFSET EQU 0fb00h\r
DSC_GDTPTR EQU 30h\r
DSC_GDTSIZ EQU 38h\r
EXTERNDEF gSmiCr3:DWORD\r
EXTERNDEF gSmiStack:DWORD\r
EXTERNDEF gSmbase:DWORD\r
+EXTERNDEF mXdSupported:BYTE\r
EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE\r
EXTERNDEF gSmiHandlerIdtr:FWORD\r
\r
or eax, BIT10\r
@@: ; as cr4.PGE is not set here, refresh cr3\r
mov cr4, eax ; in PreModifyMtrrs() to flush TLB.\r
+\r
+ cmp FeaturePcdGet (PcdCpuSmmStackGuard), 0\r
+ jz @F\r
+; Load TSS\r
+ mov byte ptr [ebp + TSS_SEGMENT + 5], 89h ; clear busy flag\r
+ mov eax, TSS_SEGMENT\r
+ ltr ax\r
+@@:\r
+\r
+; enable NXE if supported\r
+ DB 0b0h ; mov al, imm8\r
+mXdSupported DB 1\r
+ cmp al, 0\r
+ jz @SkipXd\r
+;\r
+; Check XD disable bit\r
+;\r
+ mov ecx, MSR_IA32_MISC_ENABLE\r
+ rdmsr\r
+ push edx ; save MSR_IA32_MISC_ENABLE[63-32]\r
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
+ jz @f\r
+ and dx, 0FFFBh ; clear XD Disable bit if it is set\r
+ wrmsr\r
+@@:\r
+ mov ecx, MSR_EFER\r
+ rdmsr\r
+ or ax, MSR_EFER_XD ; enable NXE\r
+ wrmsr\r
+ jmp @XdDone\r
+@SkipXd:\r
+ sub esp, 4\r
+@XdDone:\r
+\r
mov ebx, cr0\r
- or ebx, 080000000h ; enable paging\r
+ or ebx, 080010023h ; enable paging + WP + NE + MP + PE\r
mov cr0, ebx\r
lea ebx, [edi + DSC_OFFSET]\r
mov ax, [ebx + DSC_DS]\r
mov ax, [ebx + DSC_SS]\r
mov ss, eax\r
\r
- cmp FeaturePcdGet (PcdCpuSmmStackGuard), 0\r
- jz @F\r
-\r
-; Load TSS\r
- mov byte ptr [ebp + TSS_SEGMENT + 5], 89h ; clear busy flag\r
- mov eax, TSS_SEGMENT\r
- ltr ax\r
-@@:\r
; jmp _SmiHandler ; instruction is not needed\r
\r
_SmiHandler PROC\r
- mov ebx, [esp] ; CPU Index\r
-\r
+ mov ebx, [esp + 4] ; CPU Index\r
push ebx\r
mov eax, CpuSmmDebugEntry\r
call eax\r
- pop ecx\r
+ add esp, 4\r
\r
push ebx\r
mov eax, SmiRendezvous\r
call eax\r
- pop ecx\r
- \r
+ add esp, 4\r
+\r
push ebx\r
mov eax, CpuSmmDebugExit\r
call eax\r
- pop ecx\r
+ add esp, 4\r
\r
+ mov eax, offset mXdSupported\r
+ mov al, [eax]\r
+ cmp al, 0\r
+ jz @f\r
+ pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
+ test edx, BIT2\r
+ jz @f\r
+ mov ecx, MSR_IA32_MISC_ENABLE\r
+ rdmsr\r
+ or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r
+ wrmsr\r
+\r
+@@:\r
rsm\r
_SmiHandler ENDP\r
\r