Always set WP in CR0.

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmiEntry.asm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
index 8a12927300ca21e57cff0b08bca114b96c429fa5..ac1a9b48ddd0d89569a10417b3753bdf9725c5f2 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
@@ -129,7 +129,7 @@ gSmiCr3     DD      ?
 @@:                                     ; as cr4.PGE is not set here, refresh cr3\r
     mov     cr4, eax                    ; in PreModifyMtrrs() to flush TLB.\r
     mov     ebx, cr0\r
-    or      ebx, 080000000h             ; enable paging\r
+    or      ebx, 080010000h             ; enable paging + WP\r
     mov     cr0, ebx\r
     lea     ebx, [edi + DSC_OFFSET]\r
     mov     ax, [ebx + DSC_DS]\r