;------------------------------------------------------------------------------ ;\r
; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
global ASM_PFX(gPatchSmbase)\r
extern ASM_PFX(mXdSupported)\r
global ASM_PFX(gPatchXdSupported)\r
+global ASM_PFX(gPatchMsrIa32MiscEnableSupported)\r
extern ASM_PFX(gSmiHandlerIdtr)\r
\r
extern ASM_PFX(mCetSupported)\r
ASM_PFX(gPatchXdSupported):\r
cmp al, 0\r
jz @SkipXd\r
+\r
+; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit\r
+ mov al, strict byte 1 ; source operand may be patched\r
+ASM_PFX(gPatchMsrIa32MiscEnableSupported):\r
+ cmp al, 1\r
+ jz MsrIa32MiscEnableSupported\r
+\r
+; MSR_IA32_MISC_ENABLE not supported\r
+ xor edx, edx\r
+ push edx ; don't try to restore the XD Disable bit just before RSM\r
+ jmp EnableNxe\r
+\r
;\r
; Check XD disable bit\r
;\r
+MsrIa32MiscEnableSupported:\r
mov ecx, MSR_IA32_MISC_ENABLE\r
rdmsr\r
push edx ; save MSR_IA32_MISC_ENABLE[63-32]\r
test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
- jz .5\r
+ jz EnableNxe\r
and dx, 0xFFFB ; clear XD Disable bit if it is set\r
wrmsr\r
-.5:\r
+EnableNxe:\r
mov ecx, MSR_EFER\r
rdmsr\r
or ax, MSR_EFER_XD ; enable NXE\r