UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiCr3" with PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmiEntry.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index e6e29128e64eb9ebb40094f632e75f259091e33b..0023cb328d6a6e52943560058a789bf0b39272ae 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -44,8 +44,8 @@ extern ASM_PFX(CpuSmmDebugExit)
 \r
 global ASM_PFX(gcSmiHandlerTemplate)\r
 global ASM_PFX(gcSmiHandlerSize)\r
-global ASM_PFX(gSmiCr3)\r
-global ASM_PFX(gSmiStack)\r
+global ASM_PFX(gPatchSmiCr3)\r
+global ASM_PFX(gPatchSmiStack)\r
 global ASM_PFX(gPatchSmbase)\r
 global ASM_PFX(mXdSupported)\r
 extern ASM_PFX(gSmiHandlerIdtr)\r
@@ -86,15 +86,15 @@ o16 mov     es, ax
 o16 mov     fs, ax\r
 o16 mov     gs, ax\r
 o16 mov     ss, ax\r
-    DB      0xbc                   ; mov esp, imm32\r
-ASM_PFX(gSmiStack): DD 0\r
+    mov esp, strict dword 0               ; source operand will be patched\r
+ASM_PFX(gPatchSmiStack):\r
     mov     eax, ASM_PFX(gSmiHandlerIdtr)\r
     lidt    [eax]\r
     jmp     ProtFlatMode\r
 \r
 ProtFlatMode:\r
-    DB      0xb8                        ; mov eax, imm32\r
-ASM_PFX(gSmiCr3): DD 0\r
+    mov eax, strict dword 0               ; source operand will be patched\r
+ASM_PFX(gPatchSmiCr3):\r
     mov     cr3, eax\r
 ;\r
 ; Need to test for CR4 specific bit support\r