UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmbase" with PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmiEntry.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index 4d2383ff972e1d262838c0177248648b3dc80025..e6e29128e64eb9ebb40094f632e75f259091e33b 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -46,7 +46,7 @@ global ASM_PFX(gcSmiHandlerTemplate)
 global ASM_PFX(gcSmiHandlerSize)\r
 global ASM_PFX(gSmiCr3)\r
 global ASM_PFX(gSmiStack)\r
-global ASM_PFX(gSmbase)\r
+global ASM_PFX(gPatchSmbase)\r
 global ASM_PFX(mXdSupported)\r
 extern ASM_PFX(gSmiHandlerIdtr)\r
 \r
@@ -65,8 +65,8 @@ _SmiEntryPoint:
 o32 lgdt    [cs:bx]                       ; lgdt fword ptr cs:[bx]\r
     mov     ax, PROTECT_MODE_CS\r
     mov     [cs:bx-0x2],ax\r
-    DB      0x66, 0xbf                   ; mov edi, SMBASE\r
-ASM_PFX(gSmbase): DD 0\r
+    mov     edi, strict dword 0           ; source operand will be patched\r
+ASM_PFX(gPatchSmbase):\r
     lea     eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]\r
     mov     [cs:bx-0x6],eax\r
     mov     ebx, cr0\r
@@ -207,3 +207,6 @@ ASM_PFX(SmiHandler):
 \r
 ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint\r
 \r
+global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)\r
+ASM_PFX(PiSmmCpuSmiEntryFixupAddress):\r
+    ret\r