UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr0" with PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmmInit.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index bd07a6e4f53696b6af96b3b818188e598e1540bc..0f62fe4487125c38532b6b7690cbee817d818b91 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -24,7 +24,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
 \r
 global ASM_PFX(gPatchSmmCr3)\r
 global ASM_PFX(gPatchSmmCr4)\r
-global ASM_PFX(gSmmCr0)\r
+global ASM_PFX(gPatchSmmCr0)\r
 global ASM_PFX(gSmmJmpAddr)\r
 global ASM_PFX(gSmmInitStack)\r
 global ASM_PFX(gcSmiInitGdtr)\r
@@ -60,8 +60,8 @@ ASM_PFX(gPatchSmmCr4):
     rdmsr\r
     or      eax, ebx                    ; set NXE bit if NX is available\r
     wrmsr\r
-    DB      0x66, 0xb8                  ; mov eax, imm32\r
-ASM_PFX(gSmmCr0): DD 0\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr0):\r
     mov     di, PROTECT_MODE_DS\r
     mov     cr0, eax\r
     DB      0x66, 0xea                  ; jmp far [ptr48]\r