UefiCpuPkg/PiSmmCpuDxeSmm: eliminate conditional jump in IA32 SmmStartup()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmmInit.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index 9231aa5b3deda5fefdbcd4f3c772a0e60bd98633..d64fcd48d03ed8820c4a0eab069c58ec35d5b7e4 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -47,6 +47,8 @@ ASM_PFX(SmmStartup):
     mov     eax, 0x80000001             ; read capability\r
     cpuid\r
     mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.\r
+    and     ebx, BIT20                  ; extract NX capability bit\r
+    shr     ebx, 9                      ; shift bit to IA32_EFER.NXE[BIT11] position\r
     DB      0x66, 0xb8                  ; mov eax, imm32\r
 ASM_PFX(gSmmCr3): DD 0\r
     mov     cr3, eax\r
@@ -56,11 +58,8 @@ ASM_PFX(gSmmCr4): DD 0
     mov     cr4, eax\r
     mov     ecx, 0xc0000080             ; IA32_EFER MSR\r
     rdmsr\r
-    test    ebx, BIT20                  ; check NXE capability\r
-    jz      .1\r
-    or      ah, BIT3                    ; set NXE bit\r
+    or      eax, ebx                    ; set NXE bit if NX is available\r
     wrmsr\r
-.1:\r
     DB      0x66, 0xb8                  ; mov eax, imm32\r
 ASM_PFX(gSmmCr0): DD 0\r
     mov     di, PROTECT_MODE_DS\r