UefiCpuPkg/PiSmmCpuDxeSmm: Enable NXE if it's supported

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmmInit.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index a5c62e77ce5e0204989ad4e05f44f5dae282b07d..e96dd8d2392aea0d321100d455c829a8c98b182b 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -42,6 +42,11 @@ ASM_PFX(gcSmiInitGdtr):
 \r
 global ASM_PFX(SmmStartup)\r
 ASM_PFX(SmmStartup):\r
+    DB      0x66\r
+    mov     eax, 0x80000001             ; read capability\r
+    cpuid\r
+    DB      0x66\r
+    mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.\r
     DB      0x66, 0xb8\r
 ASM_PFX(gSmmCr3): DD 0\r
     mov     cr3, eax\r
@@ -50,6 +55,15 @@ ASM_PFX(gSmmCr3): DD 0
     DB      0x66, 0xb8\r
 ASM_PFX(gSmmCr4): DD 0\r
     mov     cr4, eax\r
+    DB      0x66\r
+    mov     ecx, 0xc0000080             ; IA32_EFER MSR\r
+    rdmsr\r
+    DB      0x66\r
+    test    ebx, BIT20                  ; check NXE capability\r
+    jz      .1\r
+    or      ah, BIT3                    ; set NXE bit\r
+    wrmsr\r
+.1:\r
     DB      0x66, 0xb8\r
 ASM_PFX(gSmmCr0): DD 0\r
     DB      0xbf, PROTECT_MODE_DS, 0    ; mov di, PROTECT_MODE_DS\r