\r
//\r
// Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU\r
- // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point. This size\r
- // is rounded up to nearest power of 2.\r
+ // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.\r
+ // This size is rounded up to nearest power of 2.\r
//\r
TileCodeSize = GetSmiHandlerSize ();\r
TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);\r
- TileDataSize = sizeof (SMRAM_SAVE_STATE_MAP) + sizeof (PROCESSOR_SMM_DESCRIPTOR);\r
+ TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);\r
TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);\r
TileSize = TileDataSize + TileCodeSize - 1;\r
TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);\r
DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));\r
\r
//\r
- // If the TileSize is larger than space available for the SMI Handler of CPU[i],\r
- // the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],\r
- // the ASSERT(). If this ASSERT() is triggered, then the SMI Handler size must be\r
- // reduced.\r
+ // If the TileSize is larger than space available for the SMI Handler of\r
+ // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save\r
+ // State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then\r
+ // the SMI Handler size must be reduced or the size of the extra CPU specific\r
+ // context must be reduced.\r
//\r
ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));\r
\r