UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr4" with PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index c5b67e3dc0ce4892471d8a5818928a97d6473b64..a3fd796dba4a8d6a487f13138c133f22bda86dc6 100755 (executable)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -125,6 +125,11 @@ UINTN                    mSmmCpuSmramRangeCount;
 \r
 UINT8                    mPhysicalAddressBits;\r
 \r
+//\r
+// Control register contents saved for SMM S3 resume state initialization.\r
+//\r
+UINT32                   mSmmCr4;\r
+\r
 /**\r
   Initialize IDT to setup exception handlers for SMM.\r
 \r
@@ -407,7 +412,8 @@ SmmRelocateBases (
   //\r
   gSmmCr0 = (UINT32)AsmReadCr0 ();\r
   PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);\r
-  gSmmCr4 = (UINT32)AsmReadCr4 ();\r
+  mSmmCr4 = (UINT32)AsmReadCr4 ();\r
+  PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);\r
 \r
   //\r
   // Patch GDTR for SMM base relocation\r