/** @file\r
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
\r
-Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
SmmWriteSaveState\r
};\r
\r
+///\r
+/// SMM Memory Attribute Protocol instance\r
+///\r
+EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = {\r
+ EdkiiSmmGetMemoryAttributes,\r
+ EdkiiSmmSetMemoryAttributes,\r
+ EdkiiSmmClearMemoryAttributes\r
+};\r
+\r
EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];\r
\r
//\r
//\r
BOOLEAN mSmmCodeAccessCheckEnable = FALSE;\r
\r
+//\r
+// Global copy of the PcdPteMemoryEncryptionAddressOrMask\r
+//\r
+UINT64 mAddressEncMask = 0;\r
+\r
//\r
// Spin lock used to serialize setting of SMM Code Access Check feature\r
//\r
SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL;\r
\r
+//\r
+// Saved SMM ranges information\r
+//\r
+EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;\r
+UINTN mSmmCpuSmramRangeCount;\r
+\r
+UINT8 mPhysicalAddressBits;\r
+\r
/**\r
Initialize IDT to setup exception handlers for SMM.\r
\r
)\r
{\r
UINTN Pe32Data;\r
- EFI_IMAGE_DOS_HEADER *DosHdr;\r
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
VOID *PdbPointer;\r
- UINT64 DumpIpAddress;\r
\r
//\r
// Find Image Base\r
//\r
- Pe32Data = CallerIpAddress & ~(SIZE_4KB - 1);\r
- while (Pe32Data != 0) {\r
- DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;\r
- if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {\r
- //\r
- // DOS image header is present, so read the PE header after the DOS image header.\r
- //\r
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff));\r
- //\r
- // Make sure PE header address does not overflow and is less than the initial address.\r
- //\r
- if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < CallerIpAddress)) {\r
- if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {\r
- //\r
- // It's PE image.\r
- //\r
- break;\r
- }\r
- }\r
- }\r
-\r
- //\r
- // Not found the image base, check the previous aligned address\r
- //\r
- Pe32Data -= SIZE_4KB;\r
- }\r
-\r
- DumpIpAddress = CallerIpAddress;\r
- DEBUG ((EFI_D_ERROR, "It is invoked from the instruction before IP(0x%lx)", DumpIpAddress));\r
-\r
+ Pe32Data = PeCoffSearchImageBase (CallerIpAddress);\r
if (Pe32Data != 0) {\r
+ DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *) CallerIpAddress));\r
PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);\r
if (PdbPointer != NULL) {\r
- DEBUG ((EFI_D_ERROR, " in module (%a)", PdbPointer));\r
+ DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer));\r
}\r
}\r
}\r
AsmWriteIdtr (&gcSmiIdtr);\r
ApicId = GetApicId ();\r
\r
- ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
+ ASSERT (mNumberOfCpus <= mMaxNumberOfCpus);\r
\r
for (Index = 0; Index < mNumberOfCpus; Index++) {\r
if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {\r
// Patch ASM code template with current CR0, CR3, and CR4 values\r
//\r
gSmmCr0 = (UINT32)AsmReadCr0 ();\r
- gSmmCr3 = (UINT32)AsmReadCr3 ();\r
+ PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);\r
gSmmCr4 = (UINT32)AsmReadCr4 ();\r
\r
//\r
{\r
GetAcpiCpuData ();\r
\r
+ //\r
+ // Cache a copy of UEFI memory map before we start profiling feature.\r
+ //\r
+ GetUefiMemoryMap ();\r
+\r
//\r
// Set SMM ready to lock flag and return\r
//\r
UINTN ModelId;\r
UINT32 Cr3;\r
\r
+ //\r
+ // Initialize address fixup\r
+ //\r
+ PiSmmCpuSmmInitFixupAddress ();\r
+ PiSmmCpuSmiEntryFixupAddress ();\r
+\r
//\r
// Initialize Debug Agent to support source level debug in SMM code\r
//\r
mSmmCodeAccessCheckEnable = PcdGetBool (PcdCpuSmmCodeAccessCheckEnable);\r
DEBUG ((EFI_D_INFO, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable));\r
\r
+ //\r
+ // Save the PcdPteMemoryEncryptionAddressOrMask value into a global variable.\r
+ // Make sure AddressEncMask is contained to smallest supported address field.\r
+ //\r
+ mAddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
+ DEBUG ((EFI_D_INFO, "mAddressEncMask = 0x%lx\n", mAddressEncMask));\r
+\r
//\r
// If support CPU hot plug, we need to allocate resources for possibly hot-added processors\r
//\r
\r
//\r
// Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU\r
- // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point. This size\r
- // is rounded up to nearest power of 2.\r
+ // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.\r
+ // This size is rounded up to nearest power of 2.\r
//\r
TileCodeSize = GetSmiHandlerSize ();\r
TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);\r
- TileDataSize = sizeof (SMRAM_SAVE_STATE_MAP) + sizeof (PROCESSOR_SMM_DESCRIPTOR);\r
+ TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);\r
TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);\r
TileSize = TileDataSize + TileCodeSize - 1;\r
TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);\r
DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));\r
\r
//\r
- // If the TileSize is larger than space available for the SMI Handler of CPU[i],\r
- // the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],\r
- // the ASSERT(). If this ASSERT() is triggered, then the SMI Handler size must be\r
- // reduced.\r
+ // If the TileSize is larger than space available for the SMI Handler of\r
+ // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save\r
+ // State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then\r
+ // the SMI Handler size must be reduced or the size of the extra CPU specific\r
+ // context must be reduced.\r
//\r
ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));\r
\r
);\r
ASSERT_EFI_ERROR (Status);\r
\r
+ //\r
+ // Install the SMM Memory Attribute Protocol into SMM protocol database\r
+ //\r
+ Status = gSmst->SmmInstallProtocolInterface (\r
+ &mSmmCpuHandle,\r
+ &gEdkiiSmmMemoryAttributeProtocolGuid,\r
+ EFI_NATIVE_INTERFACE,\r
+ &mSmmMemoryAttribute\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
//\r
// Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.\r
//\r
UINTN Size;\r
EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;\r
EFI_SMRAM_DESCRIPTOR *CurrentSmramRange;\r
- EFI_SMRAM_DESCRIPTOR *SmramRanges;\r
- UINTN SmramRangeCount;\r
UINTN Index;\r
UINT64 MaxSize;\r
BOOLEAN Found;\r
Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);\r
ASSERT (Status == EFI_BUFFER_TOO_SMALL);\r
\r
- SmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);\r
- ASSERT (SmramRanges != NULL);\r
+ mSmmCpuSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);\r
+ ASSERT (mSmmCpuSmramRanges != NULL);\r
\r
- Status = SmmAccess->GetCapabilities (SmmAccess, &Size, SmramRanges);\r
+ Status = SmmAccess->GetCapabilities (SmmAccess, &Size, mSmmCpuSmramRanges);\r
ASSERT_EFI_ERROR (Status);\r
\r
- SmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);\r
+ mSmmCpuSmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);\r
\r
//\r
// Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size\r
//\r
CurrentSmramRange = NULL;\r
- for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < SmramRangeCount; Index++) {\r
+ for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < mSmmCpuSmramRangeCount; Index++) {\r
//\r
// Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization\r
//\r
- if ((SmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {\r
+ if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {\r
continue;\r
}\r
\r
- if (SmramRanges[Index].CpuStart >= BASE_1MB) {\r
- if ((SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize) <= BASE_4GB) {\r
- if (SmramRanges[Index].PhysicalSize >= MaxSize) {\r
- MaxSize = SmramRanges[Index].PhysicalSize;\r
- CurrentSmramRange = &SmramRanges[Index];\r
+ if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {\r
+ if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) {\r
+ if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {\r
+ MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;\r
+ CurrentSmramRange = &mSmmCpuSmramRanges[Index];\r
}\r
}\r
}\r
\r
do {\r
Found = FALSE;\r
- for (Index = 0; Index < SmramRangeCount; Index++) {\r
- if (SmramRanges[Index].CpuStart < *SmrrBase && *SmrrBase == (SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize)) {\r
- *SmrrBase = (UINT32)SmramRanges[Index].CpuStart;\r
- *SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);\r
+ for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {\r
+ if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase &&\r
+ *SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)) {\r
+ *SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;\r
+ *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);\r
Found = TRUE;\r
- } else if ((*SmrrBase + *SmrrSize) == SmramRanges[Index].CpuStart && SmramRanges[Index].PhysicalSize > 0) {\r
- *SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);\r
+ } else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart && mSmmCpuSmramRanges[Index].PhysicalSize > 0) {\r
+ *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);\r
Found = TRUE;\r
}\r
}\r
} while (Found);\r
\r
- FreePool (SmramRanges);\r
DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize));\r
}\r
\r
//\r
for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {\r
if (Index != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {\r
-\r
+ if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {\r
+ //\r
+ // If this processor does not exist\r
+ //\r
+ continue;\r
+ }\r
//\r
// Acquire Config SMM Code Access Check spin lock. The AP will release the\r
// spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().\r
}\r
}\r
\r
-/**\r
- Set code region to be read only and data region to be execute disable.\r
-**/\r
-VOID\r
-SetRegionAttributes (\r
- VOID\r
- )\r
-{\r
- SetMemMapAttributes ();\r
-}\r
-\r
/**\r
This API provides a way to allocate memory for page table.\r
\r
Status = gSmst->SmmFreePages (Memory, UnalignedPages);\r
ASSERT_EFI_ERROR (Status);\r
}\r
- Memory = (EFI_PHYSICAL_ADDRESS) (AlignedMemory + EFI_PAGES_TO_SIZE (Pages));\r
+ Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);\r
UnalignedPages = RealPages - Pages - UnalignedPages;\r
if (UnalignedPages > 0) {\r
//\r
//\r
// Mark critical region to be read-only in page table\r
//\r
- SetRegionAttributes ();\r
+ SetMemMapAttributes ();\r
+\r
+ //\r
+ // For outside SMRAM, we only map SMM communication buffer or MMIO.\r
+ //\r
+ SetUefiMemMapAttributes ();\r
\r
//\r
// Set page table itself to be read-only\r
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