--- /dev/null
+/** @file\r
+Provides services to access SMRAM Save State Map\r
+\r
+Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiSmm.h>\r
+\r
+#include <Library/SmmCpuFeaturesLib.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/SmmServicesTableLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Register/Cpuid.h>\r
+#include <Register/SmramSaveStateMap.h>\r
+\r
+//\r
+// EFER register LMA bit\r
+//\r
+#define LMA BIT10\r
+\r
+///\r
+/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
+///\r
+#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)\r
+\r
+///\r
+/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE\r
+///\r
+#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }\r
+\r
+///\r
+/// Structure used to describe a range of registers\r
+///\r
+typedef struct {\r
+ EFI_SMM_SAVE_STATE_REGISTER Start;\r
+ EFI_SMM_SAVE_STATE_REGISTER End;\r
+ UINTN Length;\r
+} CPU_SMM_SAVE_STATE_REGISTER_RANGE;\r
+\r
+///\r
+/// Structure used to build a lookup table to retrieve the widths and offsets\r
+/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value\r
+///\r
+\r
+#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1\r
+#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2\r
+#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3\r
+#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 4\r
+\r
+typedef struct {\r
+ UINT8 Width32;\r
+ UINT8 Width64;\r
+ UINT16 Offset32;\r
+ UINT16 Offset64Lo;\r
+ UINT16 Offset64Hi;\r
+ BOOLEAN Writeable;\r
+} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;\r
+\r
+///\r
+/// Structure used to build a lookup table for the IOMisc width information\r
+///\r
+typedef struct {\r
+ UINT8 Width;\r
+ EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth;\r
+} CPU_SMM_SAVE_STATE_IO_WIDTH;\r
+\r
+///\r
+/// Variables from SMI Handler\r
+///\r
+extern UINT32 gSmbase;\r
+extern volatile UINT32 gSmiStack;\r
+extern UINT32 gSmiCr3;\r
+extern volatile UINT8 gcSmiHandlerTemplate[];\r
+extern CONST UINT16 gcSmiHandlerSize;\r
+\r
+//\r
+// Variables used by SMI Handler\r
+//\r
+IA32_DESCRIPTOR gSmiHandlerIdtr;\r
+\r
+///\r
+/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER\r
+/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
+///\r
+CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {\r
+ SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),\r
+ SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP),\r
+ SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4),\r
+ { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }\r
+};\r
+\r
+///\r
+/// Lookup table used to retrieve the widths and offsets associated with each\r
+/// supported EFI_SMM_SAVE_STATE_REGISTER value\r
+///\r
+CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {\r
+ {0, 0, 0, 0, 0, FALSE}, // Reserved\r
+\r
+ //\r
+ // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.\r
+ //\r
+ {4, 4, SMM_CPU_OFFSET (x86.SMMRevId) , SMM_CPU_OFFSET (x64.SMMRevId) , 0 , FALSE}, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1\r
+ {4, 4, SMM_CPU_OFFSET (x86.IOMisc) , SMM_CPU_OFFSET (x64.IOMisc) , 0 , FALSE}, // SMM_SAVE_STATE_REGISTER_IOMISC_INDEX = 2\r
+ {4, 8, SMM_CPU_OFFSET (x86.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE}, // SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3\r
+\r
+ //\r
+ // CPU Save State registers defined in PI SMM CPU Protocol.\r
+ //\r
+ {0, 8, 0 , SMM_CPU_OFFSET (x64.GdtBaseLoDword) , SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4\r
+ {0, 8, 0 , SMM_CPU_OFFSET (x64.IdtBaseLoDword) , SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5\r
+ {0, 8, 0 , SMM_CPU_OFFSET (x64.LdtBaseLoDword) , SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6\r
+ {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r
+ {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r
+ {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r
+ {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10\r
+\r
+ {4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20\r
+ {4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21\r
+ {4, 4, SMM_CPU_OFFSET (x86._SS) , SMM_CPU_OFFSET (x64._SS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22\r
+ {4, 4, SMM_CPU_OFFSET (x86._DS) , SMM_CPU_OFFSET (x64._DS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23\r
+ {4, 4, SMM_CPU_OFFSET (x86._FS) , SMM_CPU_OFFSET (x64._FS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24\r
+ {4, 4, SMM_CPU_OFFSET (x86._GS) , SMM_CPU_OFFSET (x64._GS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25\r
+ {0, 4, 0 , SMM_CPU_OFFSET (x64._LDTR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26\r
+ {4, 4, SMM_CPU_OFFSET (x86._TR) , SMM_CPU_OFFSET (x64._TR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27\r
+ {4, 8, SMM_CPU_OFFSET (x86._DR7) , SMM_CPU_OFFSET (x64._DR7) , SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28\r
+ {4, 8, SMM_CPU_OFFSET (x86._DR6) , SMM_CPU_OFFSET (x64._DR6) , SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29\r
+ {0, 8, 0 , SMM_CPU_OFFSET (x64._R8) , SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30\r
+ {0, 8, 0 , SMM_CPU_OFFSET (x64._R9) , SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31\r
+ {0, 8, 0 , SMM_CPU_OFFSET (x64._R10) , SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32\r
+ {0, 8, 0 , SMM_CPU_OFFSET (x64._R11) , SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33\r
+ {0, 8, 0 , SMM_CPU_OFFSET (x64._R12) , SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34\r
+ {0, 8, 0 , SMM_CPU_OFFSET (x64._R13) , SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35\r
+ {0, 8, 0 , SMM_CPU_OFFSET (x64._R14) , SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36\r
+ {0, 8, 0 , SMM_CPU_OFFSET (x64._R15) , SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37\r
+ {4, 8, SMM_CPU_OFFSET (x86._EAX) , SMM_CPU_OFFSET (x64._RAX) , SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38\r
+ {4, 8, SMM_CPU_OFFSET (x86._EBX) , SMM_CPU_OFFSET (x64._RBX) , SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39\r
+ {4, 8, SMM_CPU_OFFSET (x86._ECX) , SMM_CPU_OFFSET (x64._RCX) , SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40\r
+ {4, 8, SMM_CPU_OFFSET (x86._EDX) , SMM_CPU_OFFSET (x64._RDX) , SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41\r
+ {4, 8, SMM_CPU_OFFSET (x86._ESP) , SMM_CPU_OFFSET (x64._RSP) , SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42\r
+ {4, 8, SMM_CPU_OFFSET (x86._EBP) , SMM_CPU_OFFSET (x64._RBP) , SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43\r
+ {4, 8, SMM_CPU_OFFSET (x86._ESI) , SMM_CPU_OFFSET (x64._RSI) , SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44\r
+ {4, 8, SMM_CPU_OFFSET (x86._EDI) , SMM_CPU_OFFSET (x64._RDI) , SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45\r
+ {4, 8, SMM_CPU_OFFSET (x86._EIP) , SMM_CPU_OFFSET (x64._RIP) , SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46\r
+\r
+ {4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51\r
+ {4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52\r
+ {4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53\r
+ {0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54\r
+};\r
+\r
+///\r
+/// Lookup table for the IOMisc width information\r
+///\r
+CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] = {\r
+ { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 0\r
+ { 1, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // SMM_IO_LENGTH_BYTE = 1\r
+ { 2, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 }, // SMM_IO_LENGTH_WORD = 2\r
+ { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 3\r
+ { 4, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 }, // SMM_IO_LENGTH_DWORD = 4\r
+ { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 5\r
+ { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 6\r
+ { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 } // Undefined = 7\r
+};\r
+\r
+///\r
+/// Lookup table for the IOMisc type information\r
+///\r
+CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] = {\r
+ EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_DX = 0\r
+ EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_IN_DX = 1\r
+ EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_OUTS = 2\r
+ EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_INS = 3\r
+ (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 4\r
+ (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 5\r
+ EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_OUTS = 6\r
+ EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_INS = 7\r
+ EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_IMMEDIATE = 8\r
+ EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_OUT_IMMEDIATE = 9\r
+ (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 10\r
+ (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 11\r
+ (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 12\r
+ (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 13\r
+ (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 14\r
+ (EFI_SMM_SAVE_STATE_IO_TYPE)0 // Undefined = 15\r
+};\r
+\r
+///\r
+/// The mode of the CPU at the time an SMI occurs\r
+///\r
+UINT8 mSmmSaveStateRegisterLma;\r
+\r
+/**\r
+ Read information from the CPU save state.\r
+\r
+ @param Register Specifies the CPU register to read form the save state.\r
+\r
+ @retval 0 Register is not valid\r
+ @retval >0 Index into mSmmCpuWidthOffset[] associated with Register\r
+\r
+**/\r
+UINTN\r
+GetRegisterIndex (\r
+ IN EFI_SMM_SAVE_STATE_REGISTER Register\r
+ )\r
+{\r
+ UINTN Index;\r
+ UINTN Offset;\r
+\r
+ for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {\r
+ if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) {\r
+ return Register - mSmmCpuRegisterRanges[Index].Start + Offset;\r
+ }\r
+ Offset += mSmmCpuRegisterRanges[Index].Length;\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Read a CPU Save State register on the target processor.\r
+\r
+ This function abstracts the differences that whether the CPU Save State register is in the\r
+ IA32 CPU Save State Map or X64 CPU Save State Map.\r
+\r
+ This function supports reading a CPU Save State register in SMBase relocation handler.\r
+\r
+ @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
+ @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
+ @param[in] Width The number of bytes to read from the CPU save state.\r
+ @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
+\r
+ @retval EFI_SUCCESS The register was read from Save State.\r
+ @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
+ @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+ReadSaveStateRegisterByIndex (\r
+ IN UINTN CpuIndex,\r
+ IN UINTN RegisterIndex,\r
+ IN UINTN Width,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
+\r
+ if (RegisterIndex == 0) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ CpuSaveState = gSmst->CpuSaveState[CpuIndex];\r
+\r
+ if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
+ //\r
+ // If 32-bit mode width is zero, then the specified register can not be accessed\r
+ //\r
+ if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed\r
+ //\r
+ if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Write return buffer\r
+ //\r
+ ASSERT(CpuSaveState != NULL);\r
+ CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);\r
+ } else {\r
+ //\r
+ // If 64-bit mode width is zero, then the specified register can not be accessed\r
+ //\r
+ if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed\r
+ //\r
+ if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Write lower 32-bits of return buffer\r
+ //\r
+ CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width));\r
+ if (Width >= 4) {\r
+ //\r
+ // Write upper 32-bits of return buffer\r
+ //\r
+ CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);\r
+ }\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Read a CPU Save State register on the target processor.\r
+\r
+ This function abstracts the differences that whether the CPU Save State register is in the\r
+ IA32 CPU Save State Map or X64 CPU Save State Map.\r
+\r
+ This function supports reading a CPU Save State register in SMBase relocation handler.\r
+\r
+ @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
+ @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
+ @param[in] Width The number of bytes to read from the CPU save state.\r
+ @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
+\r
+ @retval EFI_SUCCESS The register was read from Save State.\r
+ @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
+ @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ReadSaveStateRegister (\r
+ IN UINTN CpuIndex,\r
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
+ IN UINTN Width,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ UINT32 SmmRevId;\r
+ SMRAM_SAVE_STATE_IOMISC IoMisc;\r
+ EFI_SMM_SAVE_STATE_IO_INFO *IoInfo;\r
+ VOID *IoMemAddr;\r
+\r
+ //\r
+ // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA\r
+ //\r
+ if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r
+ //\r
+ // Only byte access is supported for this register\r
+ //\r
+ if (Width != 1) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ *(UINT8 *)Buffer = mSmmSaveStateRegisterLma;\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ //\r
+ // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO\r
+ //\r
+ if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r
+ //\r
+ // Get SMM Revision ID\r
+ //\r
+ ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof(SmmRevId), &SmmRevId);\r
+\r
+ //\r
+ // See if the CPU supports the IOMisc register in the save state\r
+ //\r
+ if (SmmRevId < SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Get the IOMisc register value\r
+ //\r
+ ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof(IoMisc.Uint32), &IoMisc.Uint32);\r
+\r
+ //\r
+ // Check for the SMI_FLAG in IOMisc\r
+ //\r
+ if (IoMisc.Bits.SmiFlag == 0) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Compute index for the I/O Length and I/O Type lookup tables\r
+ //\r
+ if (mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0 || mSmmCpuIoType[IoMisc.Bits.Type] == 0) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Zero the IoInfo structure that will be returned in Buffer\r
+ //\r
+ IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer;\r
+ ZeroMem (IoInfo, sizeof(EFI_SMM_SAVE_STATE_IO_INFO));\r
+\r
+ //\r
+ // Use lookup tables to help fill in all the fields of the IoInfo structure\r
+ //\r
+ IoInfo->IoPort = (UINT16)IoMisc.Bits.Port;\r
+ IoInfo->IoWidth = mSmmCpuIoWidth[IoMisc.Bits.Length].IoWidth;\r
+ IoInfo->IoType = mSmmCpuIoType[IoMisc.Bits.Type];\r
+ if (IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_INPUT || IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT) {\r
+ ReadSaveStateRegister (CpuIndex, EFI_SMM_SAVE_STATE_REGISTER_RAX, mSmmCpuIoWidth[IoMisc.Bits.Length].Width, &IoInfo->IoData);\r
+ }\r
+ else {\r
+ ReadSaveStateRegisterByIndex(CpuIndex, SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX, sizeof(IoMemAddr), &IoMemAddr);\r
+ CopyMem(&IoInfo->IoData, IoMemAddr, mSmmCpuIoWidth[IoMisc.Bits.Length].Width);\r
+ }\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ //\r
+ // Convert Register to a register lookup table index\r
+ //\r
+ return ReadSaveStateRegisterByIndex (CpuIndex, GetRegisterIndex (Register), Width, Buffer);\r
+}\r
+\r
+/**\r
+ Write value to a CPU Save State register on the target processor.\r
+\r
+ This function abstracts the differences that whether the CPU Save State register is in the\r
+ IA32 CPU Save State Map or X64 CPU Save State Map.\r
+\r
+ This function supports writing a CPU Save State register in SMBase relocation handler.\r
+\r
+ @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
+ @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r
+ @param[in] Width The number of bytes to read from the CPU save state.\r
+ @param[in] Buffer Upon entry, this holds the new CPU register value.\r
+\r
+ @retval EFI_SUCCESS The register was written to Save State.\r
+ @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
+ @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+WriteSaveStateRegister (\r
+ IN UINTN CpuIndex,\r
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
+ IN UINTN Width,\r
+ IN CONST VOID *Buffer\r
+ )\r
+{\r
+ UINTN RegisterIndex;\r
+ SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
+\r
+ //\r
+ // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored\r
+ //\r
+ if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ //\r
+ // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported\r
+ //\r
+ if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Convert Register to a register lookup table index\r
+ //\r
+ RegisterIndex = GetRegisterIndex (Register);\r
+ if (RegisterIndex == 0) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ CpuSaveState = gSmst->CpuSaveState[CpuIndex];\r
+\r
+ //\r
+ // Do not write non-writable SaveState, because it will cause exception.\r
+ //\r
+ if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ //\r
+ // Check CPU mode\r
+ //\r
+ if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
+ //\r
+ // If 32-bit mode width is zero, then the specified register can not be accessed\r
+ //\r
+ if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed\r
+ //\r
+ if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ //\r
+ // Write SMM State register\r
+ //\r
+ ASSERT (CpuSaveState != NULL);\r
+ CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);\r
+ } else {\r
+ //\r
+ // If 64-bit mode width is zero, then the specified register can not be accessed\r
+ //\r
+ if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed\r
+ //\r
+ if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Write lower 32-bits of SMM State register\r
+ //\r
+ CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));\r
+ if (Width >= 4) {\r
+ //\r
+ // Write upper 32-bits of SMM State register\r
+ //\r
+ CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);\r
+ }\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Hook the code executed immediately after an RSM instruction on the currently\r
+ executing CPU. The mode of code executed immediately after RSM must be\r
+ detected, and the appropriate hook must be selected. Always clear the auto\r
+ HALT restart flag if it is set.\r
+\r
+ @param[in] CpuIndex The processor index for the currently\r
+ executing CPU.\r
+ @param[in] CpuState Pointer to SMRAM Save State Map for the\r
+ currently executing CPU.\r
+ @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
+ 32-bit mode from 64-bit SMM.\r
+ @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
+ same mode as SMM.\r
+\r
+ @retval The value of the original instruction pointer before it was hooked.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+HookReturnFromSmm (\r
+ IN UINTN CpuIndex,\r
+ SMRAM_SAVE_STATE_MAP *CpuState,\r
+ UINT64 NewInstructionPointer32,\r
+ UINT64 NewInstructionPointer\r
+ )\r
+{\r
+ UINT64 OriginalInstructionPointer;\r
+\r
+ OriginalInstructionPointer = SmmCpuFeaturesHookReturnFromSmm (\r
+ CpuIndex,\r
+ CpuState,\r
+ NewInstructionPointer32,\r
+ NewInstructionPointer\r
+ );\r
+ if (OriginalInstructionPointer != 0) {\r
+ return OriginalInstructionPointer;\r
+ }\r
+\r
+ if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
+ OriginalInstructionPointer = (UINT64)CpuState->x86._EIP;\r
+ CpuState->x86._EIP = (UINT32)NewInstructionPointer;\r
+ //\r
+ // Clear the auto HALT restart flag so the RSM instruction returns\r
+ // program control to the instruction following the HLT instruction.\r
+ //\r
+ if ((CpuState->x86.AutoHALTRestart & BIT0) != 0) {\r
+ CpuState->x86.AutoHALTRestart &= ~BIT0;\r
+ }\r
+ } else {\r
+ OriginalInstructionPointer = CpuState->x64._RIP;\r
+ if ((CpuState->x64.IA32_EFER & LMA) == 0) {\r
+ CpuState->x64._RIP = (UINT32)NewInstructionPointer32;\r
+ } else {\r
+ CpuState->x64._RIP = (UINT32)NewInstructionPointer;\r
+ }\r
+ //\r
+ // Clear the auto HALT restart flag so the RSM instruction returns\r
+ // program control to the instruction following the HLT instruction.\r
+ //\r
+ if ((CpuState->x64.AutoHALTRestart & BIT0) != 0) {\r
+ CpuState->x64.AutoHALTRestart &= ~BIT0;\r
+ }\r
+ }\r
+ return OriginalInstructionPointer;\r
+}\r
+\r
+/**\r
+ Get the size of the SMI Handler in bytes.\r
+\r
+ @retval The size, in bytes, of the SMI Handler.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+GetSmiHandlerSize (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Size;\r
+\r
+ Size = SmmCpuFeaturesGetSmiHandlerSize ();\r
+ if (Size != 0) {\r
+ return Size;\r
+ }\r
+ return gcSmiHandlerSize;\r
+}\r
+\r
+/**\r
+ Install the SMI handler for the CPU specified by CpuIndex. This function\r
+ is called by the CPU that was elected as monarch during System Management\r
+ Mode initialization.\r
+\r
+ @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r
+ The value must be between 0 and the NumberOfCpus field\r
+ in the System Management System Table (SMST).\r
+ @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r
+ @param[in] SmiStack The stack to use when an SMI is processed by the\r
+ the CPU specified by CpuIndex.\r
+ @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r
+ processed by the CPU specified by CpuIndex.\r
+ @param[in] GdtBase The base address of the GDT to use when an SMI is\r
+ processed by the CPU specified by CpuIndex.\r
+ @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r
+ processed by the CPU specified by CpuIndex.\r
+ @param[in] IdtBase The base address of the IDT to use when an SMI is\r
+ processed by the CPU specified by CpuIndex.\r
+ @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r
+ processed by the CPU specified by CpuIndex.\r
+ @param[in] Cr3 The base address of the page tables to use when an SMI\r
+ is processed by the CPU specified by CpuIndex.\r
+**/\r
+VOID\r
+EFIAPI\r
+InstallSmiHandler (\r
+ IN UINTN CpuIndex,\r
+ IN UINT32 SmBase,\r
+ IN VOID *SmiStack,\r
+ IN UINTN StackSize,\r
+ IN UINTN GdtBase,\r
+ IN UINTN GdtSize,\r
+ IN UINTN IdtBase,\r
+ IN UINTN IdtSize,\r
+ IN UINT32 Cr3\r
+ )\r
+{\r
+ if (SmmCpuFeaturesGetSmiHandlerSize () != 0) {\r
+ //\r
+ // Install SMI handler provided by library\r
+ //\r
+ SmmCpuFeaturesInstallSmiHandler (\r
+ CpuIndex,\r
+ SmBase,\r
+ SmiStack,\r
+ StackSize,\r
+ GdtBase,\r
+ GdtSize,\r
+ IdtBase,\r
+ IdtSize,\r
+ Cr3\r
+ );\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Initialize values in template before copy\r
+ //\r
+ gSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN));\r
+ gSmiCr3 = Cr3;\r
+ gSmbase = SmBase;\r
+ gSmiHandlerIdtr.Base = IdtBase;\r
+ gSmiHandlerIdtr.Limit = (UINT16)(IdtSize - 1);\r
+\r
+ //\r
+ // Set the value at the top of the CPU stack to the CPU Index\r
+ //\r
+ *(UINTN*)(UINTN)gSmiStack = CpuIndex;\r
+\r
+ //\r
+ // Copy template to CPU specific SMI handler location\r
+ //\r
+ CopyMem (\r
+ (VOID*)(UINTN)(SmBase + SMM_HANDLER_OFFSET),\r
+ (VOID*)gcSmiHandlerTemplate,\r
+ gcSmiHandlerSize\r
+ );\r
+}\r
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