UefiCpuPkg: PiSmmCpuDxeSmm skip MSR_IA32_MISC_ENABLE manipulation on AMD

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmiEntry.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 8bfba55b5d082dcb9b51f257c832f2aff425f345..0e154e5db9490640a809808bb2506065f7e4d1be 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -1,5 +1,6 @@
 ;------------------------------------------------------------------------------ ;\r
 ; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ; Module Name:\r
@@ -67,6 +68,7 @@ extern ASM_PFX(CpuSmmDebugExit)
 global ASM_PFX(gPatchSmbase)\r
 extern ASM_PFX(mXdSupported)\r
 global ASM_PFX(gPatchXdSupported)\r
+global ASM_PFX(gPatchMsrIa32MiscEnableSupported)\r
 global ASM_PFX(gPatchSmiStack)\r
 global ASM_PFX(gPatchSmiCr3)\r
 global ASM_PFX(gPatch5LevelPagingNeeded)\r
@@ -152,18 +154,32 @@ SkipEnable5LevelPaging:
 ASM_PFX(gPatchXdSupported):\r
     cmp     al, 0\r
     jz      @SkipXd\r
+\r
+; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit\r
+    mov     al, strict byte 1           ; source operand may be patched\r
+ASM_PFX(gPatchMsrIa32MiscEnableSupported):\r
+    cmp     al, 1\r
+    jz      MsrIa32MiscEnableSupported\r
+\r
+; MSR_IA32_MISC_ENABLE not supported\r
+    sub     esp, 4\r
+    xor     rdx, rdx\r
+    push    rdx                         ; don't try to restore the XD Disable bit just before RSM\r
+    jmp     EnableNxe\r
+\r
 ;\r
 ; Check XD disable bit\r
 ;\r
+MsrIa32MiscEnableSupported:\r
     mov     ecx, MSR_IA32_MISC_ENABLE\r
     rdmsr\r
     sub     esp, 4\r
     push    rdx                        ; save MSR_IA32_MISC_ENABLE[63-32]\r
     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]\r
-    jz      .0\r
+    jz      EnableNxe\r
     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set\r
     wrmsr\r
-.0:\r
+EnableNxe:\r
     mov     ecx, MSR_EFER\r
     rdmsr\r
     or      ax, MSR_EFER_XD            ; enable NXE\r