UefiCpuPkg/PiSmmCpuDxeSmm: patch "XdSupported" with PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmiEntry.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index c3c094ff9f7e9882807e71038280b3b801c63c4c..5d731e2280957a418f53b5707a60414ca9b7ab73 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -53,10 +53,11 @@ extern ASM_PFX(gSmiHandlerIdtr)
 extern ASM_PFX(CpuSmmDebugEntry)\r
 extern ASM_PFX(CpuSmmDebugExit)\r
 \r
-global ASM_PFX(gSmbase)\r
-global ASM_PFX(mXdSupported)\r
-global ASM_PFX(gSmiStack)\r
-global ASM_PFX(gSmiCr3)\r
+global ASM_PFX(gPatchSmbase)\r
+extern ASM_PFX(mXdSupported)\r
+global ASM_PFX(gPatchXdSupported)\r
+global ASM_PFX(gPatchSmiStack)\r
+global ASM_PFX(gPatchSmiCr3)\r
 global ASM_PFX(gcSmiHandlerTemplate)\r
 global ASM_PFX(gcSmiHandlerSize)\r
 \r
@@ -75,8 +76,8 @@ _SmiEntryPoint:
 o32 lgdt    [cs:bx]                       ; lgdt fword ptr cs:[bx]\r
     mov     ax, PROTECT_MODE_CS\r
     mov     [cs:bx-0x2],ax\r
-    DB      0x66, 0xbf                   ; mov edi, SMBASE\r
-ASM_PFX(gSmbase): DD 0\r
+    mov     edi, strict dword 0           ; source operand will be patched\r
+ASM_PFX(gPatchSmbase):\r
     lea     eax, [edi + (@ProtectedMode - _SmiEntryPoint) + 0x8000]\r
     mov     [cs:bx-0x6],eax\r
     mov     ebx, cr0\r
@@ -96,14 +97,14 @@ o16 mov     es, ax
 o16 mov     fs, ax\r
 o16 mov     gs, ax\r
 o16 mov     ss, ax\r
-    DB      0xbc                   ; mov esp, imm32\r
-ASM_PFX(gSmiStack): DD 0\r
+    mov esp, strict dword 0               ; source operand will be patched\r
+ASM_PFX(gPatchSmiStack):\r
     jmp     ProtFlatMode\r
 \r
 BITS 64\r
 ProtFlatMode:\r
-    DB      0xb8                        ; mov eax, offset gSmiCr3\r
-ASM_PFX(gSmiCr3): DD 0\r
+    mov eax, strict dword 0               ; source operand will be patched\r
+ASM_PFX(gPatchSmiCr3):\r
     mov     cr3, rax\r
     mov     eax, 0x668                   ; as cr4.PGE is not set here, refresh cr3\r
     mov     cr4, rax                    ; in PreModifyMtrrs() to flush TLB.\r
@@ -118,8 +119,8 @@ ASM_PFX(gSmiCr3): DD 0
     ltr     ax\r
 \r
 ; enable NXE if supported\r
-    DB      0xb0                        ; mov al, imm8\r
-ASM_PFX(mXdSupported):     DB      1\r
+    mov     al, strict byte 1           ; source operand may be patched\r
+ASM_PFX(gPatchXdSupported):\r
     cmp     al, 0\r
     jz      @SkipXd\r
 ;\r
@@ -158,7 +159,8 @@ Base:
     mov     cr0, rbx\r
     retf\r
 @LongMode:                              ; long mode (64-bit code) starts here\r
-    mov     rax, ASM_PFX(gSmiHandlerIdtr)\r
+    mov     rax, strict qword 0         ;  mov     rax, ASM_PFX(gSmiHandlerIdtr)\r
+SmiHandlerIdtrAbsAddr:\r
     lidt    [rax]\r
     lea     ebx, [rdi + DSC_OFFSET]\r
     mov     ax, [rbx + DSC_DS]\r
@@ -169,7 +171,9 @@ Base:
     mov     gs, eax\r
     mov     ax, [rbx + DSC_SS]\r
     mov     ss, eax\r
-;   jmp     _SmiHandler                 ; instruction is not needed\r
+    mov     rax, strict qword 0         ;   mov     rax, _SmiHandler\r
+_SmiHandlerAbsAddr:\r
+    jmp     rax\r
 \r
 _SmiHandler:\r
     mov     rbx, [rsp + 0x8]             ; rcx <- CpuIndex\r
@@ -184,16 +188,13 @@ _SmiHandler:
     add     rsp, -0x20\r
 \r
     mov     rcx, rbx\r
-    mov     rax, CpuSmmDebugEntry\r
-    call    rax\r
+    call    ASM_PFX(CpuSmmDebugEntry)\r
 \r
     mov     rcx, rbx\r
-    mov     rax, SmiRendezvous          ; rax <- absolute addr of SmiRedezvous\r
-    call    rax\r
+    call    ASM_PFX(SmiRendezvous)\r
 \r
     mov     rcx, rbx\r
-    mov     rax, CpuSmmDebugExit\r
-    call    rax\r
+    call    ASM_PFX(CpuSmmDebugExit)\r
 \r
     add     rsp, 0x20\r
 \r
@@ -205,7 +206,7 @@ _SmiHandler:
 \r
     add     rsp, 0x200\r
 \r
-    mov     rax, ASM_PFX(mXdSupported)\r
+    lea     rax, [ASM_PFX(mXdSupported)]\r
     mov     al, [rax]\r
     cmp     al, 0\r
     jz      .1\r
@@ -220,5 +221,15 @@ _SmiHandler:
 .1:\r
     rsm\r
 \r
-gcSmiHandlerSize    DW      $ - _SmiEntryPoint\r
+ASM_PFX(gcSmiHandlerSize)    DW      $ - _SmiEntryPoint\r
 \r
+global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)\r
+ASM_PFX(PiSmmCpuSmiEntryFixupAddress):\r
+    lea    rax, [ASM_PFX(gSmiHandlerIdtr)]\r
+    lea    rcx, [SmiHandlerIdtrAbsAddr]\r
+    mov    qword [rcx - 8], rax\r
+\r
+    lea    rax, [_SmiHandler]\r
+    lea    rcx, [_SmiHandlerAbsAddr]\r
+    mov    qword [rcx - 8], rax\r
+    ret\r