UefiCpuPkg: Update PiSmmCpuDxeSmm pass XCODE5 tool chain

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmmInit.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 9d05e2cb0582b3fd648fcea066d0a85654dc8c83..2701689c3de4afa75fbac1a107a557bc974d7339 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -60,7 +60,7 @@ ASM_PFX(gSmmCr4): DD 0
 ASM_PFX(gSmmCr0): DD 0\r
     mov     cr0, rax                    ; enable protected mode & paging\r
     DB      0x66, 0xea                   ; far jmp to long mode\r
-ASM_PFX(gSmmJmpAddr): DQ @LongMode\r
+ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode\r
 @LongMode:                              ; long-mode starts here\r
     DB      0x48, 0xbc                   ; mov rsp, imm64\r
 ASM_PFX(gSmmInitStack): DQ 0\r
@@ -99,7 +99,7 @@ ASM_PFX(gcSmmInitTemplate):
     sub ebp, 0x30000\r
     jmp ebp\r
 @L1:\r
-    DQ      ASM_PFX(SmmStartup)\r
+    DQ     0; ASM_PFX(SmmStartup)\r
 \r
 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)\r
 \r
@@ -128,3 +128,14 @@ ASM_PFX(mRebasedFlagAddr32): dd 0
     ;\r
     db      0xff, 0x25\r
 ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0\r
+\r
+global ASM_PFX(PiSmmCpuSmmInitFixupAddress)\r
+ASM_PFX(PiSmmCpuSmmInitFixupAddress):\r
+    lea    rax, [@LongMode]\r
+    lea    rcx, [ASM_PFX(gSmmJmpAddr)]\r
+    mov    qword [rcx], rax\r
+\r
+    lea    rax, [ASM_PFX(SmmStartup)]\r
+    lea    rcx, [@L1]\r
+    mov    qword [rcx], rax\r
+    ret\r