UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr4" with PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmmInit.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 2df22a1f6cd1591a8aef3100d0de46c93809b731..971bd118132fc7c29ef8a83e46a84f825ef9a577 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -23,7 +23,7 @@ extern ASM_PFX(mRebasedFlag)
 extern ASM_PFX(mSmmRelocationOriginalAddress)\r
 \r
 global ASM_PFX(gPatchSmmCr3)\r
-global ASM_PFX(gSmmCr4)\r
+global ASM_PFX(gPatchSmmCr4)\r
 global ASM_PFX(gSmmCr0)\r
 global ASM_PFX(gSmmJmpAddr)\r
 global ASM_PFX(gSmmInitStack)\r
@@ -51,8 +51,8 @@ ASM_PFX(SmmStartup):
 ASM_PFX(gPatchSmmCr3):\r
     mov     cr3, eax\r
 o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
-    DB      0x66, 0xb8                   ; mov eax, imm32\r
-ASM_PFX(gSmmCr4): DD 0\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr4):\r
     or      ah,  2                      ; enable XMM registers access\r
     mov     cr4, eax\r
     mov     ecx, 0xc0000080             ; IA32_EFER MSR\r