//\r
// Generate PAE page table for the first 4GB memory space\r
//\r
- Pages = Gen4GPageTable (1);\r
+ Pages = Gen4GPageTable (1, FALSE);\r
\r
//\r
// Fill Page-Table-Level4 (PML4) entry\r
//\r
PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (1));\r
- *PTEntry = Pages + IA32_PG_P;\r
+ *PTEntry = Pages | PAGE_ATTRIBUTE_BITS;\r
ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));\r
\r
//\r
//\r
// Link & Record the current uplink\r
//\r
- *Uplink = Address | IA32_PG_P | IA32_PG_RW;\r
+ *Uplink = Address | PAGE_ATTRIBUTE_BITS;\r
mPFPageUplink[mPFPageIndex] = Uplink;\r
\r
mPFPageIndex = (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT;\r
// PTE\r
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
for (Index = 0; Index < 512; Index++) {\r
- PageTable[Index] = Address | IA32_PG_RW | IA32_PG_P;\r
+ PageTable[Index] = Address | PAGE_ATTRIBUTE_BITS;\r
if (!IsAddressValid (Address, &Nx)) {\r
- PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+ PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
}\r
if (Nx && mXdSupported) {\r
PageTable[Index] = PageTable[Index] | IA32_PG_NX;\r
//\r
// Patch to remove present flag and rw flag.\r
//\r
- PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));\r
+ PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
}\r
//\r
// Set XD bit to 1\r
//\r
// Add present flag or clear XD flag to make page fault handler succeed.\r
//\r
- PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);\r
+ PageTable[PTIndex] |= (UINT64)(PAGE_ATTRIBUTE_BITS);\r
if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
//\r
// If page fault is caused by instruction fetch, clear XD bit in the entry.\r