UefiCpuPkg/CpuDxe: Enable protection for newly added page table

[mirror_edk2.git] / UefiCpuPkg / SecCore / SecMain.c

diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index ec252cf719f5f72998c0ca8af74085b2ff6859aa..c241d3704af72b9702b15fbcc277358aa195d678 100644 (file)
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -1,7 +1,7 @@
 /** @file\r
   C functions in SEC\r
 \r
-  Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -21,6 +21,14 @@ EFI_PEI_TEMPORARY_RAM_DONE_PPI gSecTemporaryRamDonePpi = {
 EFI_SEC_PLATFORM_INFORMATION_PPI  mSecPlatformInformationPpi = { SecPlatformInformation };\r
 \r
 EFI_PEI_PPI_DESCRIPTOR            mPeiSecPlatformInformationPpi[] = {\r
+  {\r
+    //\r
+    // SecPerformance PPI notify descriptor.\r
+    //\r
+    EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,\r
+    &gPeiSecPerformancePpiGuid,\r
+    (VOID *) (UINTN) SecPerformancePpiCallBack\r
+  },\r
   {\r
     EFI_PEI_PPI_DESCRIPTOR_PPI,\r
     &gEfiTemporaryRamDonePpiGuid,\r
@@ -49,11 +57,50 @@ UINT64  mIdtEntryTemplate = 0xffff8e000010ffe4ULL;
 \r
 **/\r
 VOID\r
+NORETURN\r
 EFIAPI\r
 SecStartupPhase2(\r
   IN VOID                     *Context\r
   );\r
 \r
+/**\r
+  Entry point of the notification callback function itself within the PEIM.\r
+  It is to get SEC performance data and build HOB to convey the SEC performance\r
+  data to DXE phase.\r
+\r
+  @param  PeiServices      Indirect reference to the PEI Services Table.\r
+  @param  NotifyDescriptor Address of the notification descriptor data structure.\r
+  @param  Ppi              Address of the PPI that was installed.\r
+\r
+  @return Status of the notification.\r
+          The status code returned from this function is ignored.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecPerformancePpiCallBack (\r
+  IN EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *Ppi\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  PEI_SEC_PERFORMANCE_PPI       *SecPerf;\r
+  FIRMWARE_SEC_PERFORMANCE      Performance;\r
+\r
+  SecPerf = (PEI_SEC_PERFORMANCE_PPI *) Ppi;\r
+  Status = SecPerf->GetPerformance ((CONST EFI_PEI_SERVICES **) PeiServices, SecPerf, &Performance);\r
+  if (!EFI_ERROR (Status)) {\r
+    BuildGuidDataHob (\r
+      &gEfiFirmwarePerformanceGuid,\r
+      &Performance,\r
+      sizeof (FIRMWARE_SEC_PERFORMANCE)\r
+    );\r
+    DEBUG ((DEBUG_INFO, "FPDT: SEC Performance Hob ResetEnd = %ld\n", Performance.ResetEnd));\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
 /**\r
 \r
   Entry point to the C language phase of SEC. After the SEC assembly\r
@@ -142,7 +189,7 @@ SecStartup (
   //\r
   SecCoreData.DataSize               = (UINT16) sizeof (EFI_SEC_PEI_HAND_OFF);\r
   SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;\r
-  SecCoreData.BootFirmwareVolumeSize = (UINTN)(0x100000000ULL - (UINTN) BootFirmwareVolume);\r
+  SecCoreData.BootFirmwareVolumeSize = (UINTN)((EFI_FIRMWARE_VOLUME_HEADER *) BootFirmwareVolume)->FvLength;\r
   SecCoreData.TemporaryRamBase       = (VOID*)(UINTN) TempRamBase;\r
   SecCoreData.TemporaryRamSize       = SizeOfRam;\r
   SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
@@ -167,6 +214,7 @@ SecStartup (
 \r
 **/\r
 VOID\r
+NORETURN\r
 EFIAPI\r
 SecStartupPhase2(\r
   IN VOID                     *Context\r
@@ -228,6 +276,12 @@ SecStartupPhase2(
     ASSERT (SecCoreData->PeiTemporaryRamSize > Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
     SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
     SecCoreData->PeiTemporaryRamSize = SecCoreData->PeiTemporaryRamSize - Index * sizeof (EFI_PEI_PPI_DESCRIPTOR);\r
+    //\r
+    // Adjust the Base and Size to be 8-byte aligned as HOB which has 8byte aligned requirement\r
+    // will be built based on them in PEI phase.\r
+    //\r
+    SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);\r
+    SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07;\r
   } else {\r
     //\r
     // No addition PPI, PpiList directly point to the common PPI list.\r
@@ -235,6 +289,14 @@ SecStartupPhase2(
     PpiList = &mPeiSecPlatformInformationPpi[0];\r
   }\r
 \r
+  DEBUG ((\r
+    DEBUG_INFO,\r
+    "%a() Stack Base: 0x%p, Stack Size: 0x%x\n",\r
+    __FUNCTION__,\r
+    SecCoreData->StackBase,\r
+    (UINT32) SecCoreData->StackSize\r
+    ));\r
+\r
   //\r
   // Report Status Code to indicate transferring to PEI core\r
   //\r
@@ -252,7 +314,7 @@ SecStartupPhase2(
   //\r
   // Should not come here.\r
   //\r
-  return;\r
+  UNREACHABLE ();\r
 }\r
 \r
 /**\r
@@ -271,6 +333,11 @@ SecTemporaryRamDone (
 {\r
   BOOLEAN  State;\r
 \r
+  //\r
+  // Republish Sec Platform Information(2) PPI\r
+  //\r
+  RepublishSecPlatformInformationPpi ();\r
+\r
   //\r
   // Migrate DebugAgentContext.\r
   //\r