PACKAGE_NAME = UefiCpuPkg\r
PACKAGE_UNI_FILE = UefiCpuPkg.uni\r
PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23\r
- PACKAGE_VERSION = 0.3\r
+ PACKAGE_VERSION = 0.90\r
\r
[Includes]\r
Include\r
## @libraryclass Defines some routines that are used to register/manage/program\r
## CPU features.\r
##\r
- UefiCpuLib|Include/Library/RegisterCpuFeaturesLib.h\r
+ RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h\r
\r
[LibraryClasses.IA32, LibraryClasses.X64]\r
## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.\r
##\r
MpInitLib|Include/Library/MpInitLib.h\r
\r
- ## @libraryclass Provides services to access Microcode region on flash device.\r
- #\r
- MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h\r
-\r
[Guids]\r
gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r
gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}\r
\r
- ## Include/Guid/MicrocodeFmp.h\r
- gMicrocodeFmpImageTypeIdGuid = { 0x96d4fdcd, 0x1502, 0x424d, { 0x9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } }\r
-\r
## Include/Guid/CpuFeaturesSetDone.h\r
gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}\r
\r
[PcdsFeatureFlag]\r
## Indicates if SMM Profile will be enabled.\r
# If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
+ # It could not be enabled at the same time with SMM static page table feature (PcdCpuSmmStaticPageTable).\r
# This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r
# TRUE - SMM Profile will be enabled.<BR>\r
# FALSE - SMM Profile will be disabled.<BR>\r
# @Prompt Lock SMM Feature Control MSR.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B\r
\r
+[PcdsFixedAtBuild]\r
+ ## List of exception vectors which need switching stack.\r
+ # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
+ # By default exception #DD(8), #PF(14) are supported.\r
+ # @Prompt Specify exception vectors which need switching stack.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000\r
+\r
+ ## Size of good stack for an exception.\r
+ # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
+ # @Prompt Specify size of good stack of exception which need switching stack.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001\r
+\r
[PcdsFixedAtBuild, PcdsPatchableInModule]\r
## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r
# @Prompt Configure base address of CPU Local APIC\r
# @Prompt MSEG size.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112\r
\r
- ## Specifies the supported CPU features bit in array\r
- # @Prompt Supported CPU features\r
+ ## Specifies the supported CPU features bit in array.\r
+ # @Prompt Supported CPU features.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016\r
\r
- ## Specifies if CPU features will be initialized after SMM relocation\r
- # @Prompt if CPU features will be initialized after SMM relocation\r
+ ## Specifies if CPU features will be initialized after SMM relocation.\r
+ # @Prompt If CPU features will be initialized after SMM relocation.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C\r
\r
- ## Specifies if CPU features will be initialized during S3 resume\r
- # @Prompt if CPU features will be initialized during S3 resume\r
+ ## Specifies if CPU features will be initialized during S3 resume.\r
+ # @Prompt If CPU features will be initialized during S3 resume.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r
\r
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r
\r
## Indicates if SMM uses static page table.\r
- # If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.<BR><BR>\r
- # This flag only impacts X64 build, because SMM alway builds static page table for IA32.\r
+ # If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.\r
+ # This flag only impacts X64 build, because SMM always builds static page table for IA32.\r
+ # It could not be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r
+ # It could not be enabled also at the same time with heap guard feature for SMM\r
+ # (PcdHeapGuardPropertyMask in MdeModulePkg).<BR><BR>\r
# TRUE - SMM uses static page table for all memory.<BR>\r
# FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.<BR>\r
# @Prompt Use static page table for all memory in SMM.\r
# @ValidList 0x80000001 | 0\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019\r
\r
+ ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>\r
+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
+ # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
+ # Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>\r
+ # 0x0 - 4K.<BR>\r
+ # 0x1 - 8K.<BR>\r
+ # 0x2 - 16K.<BR>\r
+ # 0x3 - 32K.<BR>\r
+ # 0x4 - 64K.<BR>\r
+ # 0x5 - 128K.<BR>\r
+ # 0x6 - 256K.<BR>\r
+ # 0x7 - 512K.<BR>\r
+ # 0x8 - 1M.<BR>\r
+ # 0x9 - 2M.<BR>\r
+ # 0xA - 4M.<BR>\r
+ # 0xB - 8M.<BR>\r
+ # 0xC - 16M.<BR>\r
+ # 0xD - 32M.<BR>\r
+ # 0xE - 64M.<BR>\r
+ # 0xF - 128M.<BR>\r
+ # @Prompt The memory size used for processor trace if processor trace is enabled.\r
+ # @ValidRange 0x80000001 | 0 - 0xF\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012\r
+\r
+ ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>\r
+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
+ # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
+ # Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>\r
+ # 0 - Single Range output scheme.<BR>\r
+ # 1 - ToPA(Table of physical address) scheme.<BR>\r
+ # @Prompt The processor trace output scheme used when processor trace is enabled.\r
+ # @ValidRange 0x80000001 | 0 - 1\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015\r
+\r
[UserExtensions.TianoCore."ExtraFiles"]\r
UefiCpuPkgExtra.uni\r
projects / mirror_edk2.git / blobdiff