## @file UefiCpuPkg.dec\r
# This Package provides UEFI compatible CPU modules and libraries.\r
#\r
-# Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials are licensed and made available under\r
# the terms and conditions of the BSD License which accompanies this distribution.\r
PACKAGE_NAME = UefiCpuPkg\r
PACKAGE_UNI_FILE = UefiCpuPkg.uni\r
PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23\r
- PACKAGE_VERSION = 0.3\r
+ PACKAGE_VERSION = 0.90\r
\r
[Includes]\r
Include\r
##\r
UefiCpuLib|Include/Library/UefiCpuLib.h\r
\r
+ ## @libraryclass Defines some routines that are used to register/manage/program\r
+ ## CPU features.\r
+ ##\r
+ RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h\r
+\r
[LibraryClasses.IA32, LibraryClasses.X64]\r
## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.\r
##\r
##\r
SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h\r
\r
+ ## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.\r
+ ##\r
+ MpInitLib|Include/Library/MpInitLib.h\r
+\r
[Guids]\r
gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r
+ gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}\r
+\r
+ ## Include/Guid/CpuFeaturesSetDone.h\r
+ gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}\r
+\r
+ ## Include/Guid/CpuFeaturesInitDone.h\r
+ gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}\r
\r
[Protocols]\r
## Include/Protocol/SmmCpuService.h\r
gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r
\r
+ ## Include/Protocol/SmMonitorInit.h\r
+ gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}\r
+\r
#\r
# [Error.gUefiCpuPkgTokenSpaceGuid]\r
# 0x80000001 | Invalid value provided.\r
[PcdsFeatureFlag]\r
## Indicates if SMM Profile will be enabled.\r
# If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
+ # It could not be enabled at the same time with SMM static page table feature (PcdCpuSmmStaticPageTable).\r
# This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r
# TRUE - SMM Profile will be enabled.<BR>\r
# FALSE - SMM Profile will be disabled.<BR>\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108\r
\r
## Indicates if SMM Stack Guard will be enabled.\r
- # If enabled, stack overflow in SMM can be caught which eases debugging.<BR><BR>\r
+ # If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>\r
# TRUE - SMM Stack Guard will be enabled.<BR>\r
# FALSE - SMM Stack Guard will be disabled.<BR>\r
# @Prompt Enable SMM Stack Guard.\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE|BOOLEAN|0x1000001C\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C\r
\r
## Indicates if BSP election in SMM will be enabled.\r
# If enabled, a BSP will be dynamically elected among all processors in each SMI.\r
# @Prompt Lock SMM Feature Control MSR.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B\r
\r
+[PcdsFixedAtBuild]\r
+ ## List of exception vectors which need switching stack.\r
+ # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
+ # By default exception #DD(8), #PF(14) are supported.\r
+ # @Prompt Specify exception vectors which need switching stack.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000\r
+\r
+ ## Size of good stack for an exception.\r
+ # This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
+ # @Prompt Specify size of good stack of exception which need switching stack.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001\r
+\r
[PcdsFixedAtBuild, PcdsPatchableInModule]\r
## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r
# @Prompt Configure base address of CPU Local APIC\r
# @Prompt Configure delay value after send an INIT IPI\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002\r
\r
- ## Specifies max supported number of Logical Processors.\r
- # @Prompt Configure max supported number of Logical Processors\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002\r
-\r
## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must\r
## aligns the address on a 4-KByte boundary.\r
# @Prompt Configure stack size for Application Processor (AP)\r
# @Prompt Processor stack size in SMM.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105\r
\r
- ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r
- # @Prompt AP synchronization timeout value in SMM.\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r
-\r
## Indicates if SMM Code Access Check is enabled.\r
# If enabled, the SMM handler cannot execute the code outside SMM regions.\r
# This PCD is suggested to TRUE in production image.<BR><BR>\r
# @Prompt SMM Code Access Check.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013\r
\r
- ## Indicates the CPU synchronization method used when processing an SMI.\r
- # 0x00 - Traditional CPU synchronization method.<BR>\r
- # 0x01 - Relaxed CPU synchronization method.<BR>\r
- # @Prompt SMM CPU Synchronization Method.\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014\r
-\r
## Specifies the number of variable MTRRs reserved for OS use. The default number of\r
# MTRRs reserved for OS use is 2.\r
# @Prompt Number of reserved variable MTRRs.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015\r
\r
+ ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.\r
+ # @Prompt STM exception stack size.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111\r
+\r
+ ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.\r
+ # @Prompt MSEG size.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112\r
+\r
+ ## Specifies the supported CPU features bit in array.\r
+ # @Prompt Supported CPU features.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016\r
+\r
+ ## Specifies if CPU features will be initialized after SMM relocation.\r
+ # @Prompt If CPU features will be initialized after SMM relocation.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C\r
+\r
+ ## Specifies if CPU features will be initialized during S3 resume.\r
+ # @Prompt If CPU features will be initialized during S3 resume.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r
+\r
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
+ ## Specifies max supported number of Logical Processors.\r
+ # @Prompt Configure max supported number of Logical Processors\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002\r
## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.\r
# @Prompt Timeout for the BSP to detect all APs for the first time.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004\r
## Specifies the size of the microcode Region.\r
# @Prompt Microcode Region size.\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006\r
+ ## Specifies the AP wait loop state during POST phase.\r
+ # The value is defined as below.<BR><BR>\r
+ # 1: Place AP in the Hlt-Loop state.<BR>\r
+ # 2: Place AP in the Mwait-Loop state.<BR>\r
+ # 3: Place AP in the Run-Loop state.<BR>\r
+ # @Prompt The AP wait loop state.\r
+ # @ValidRange 0x80000001 | 1 - 3\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006\r
+ ## Specifies the AP target C-state for Mwait during POST phase.\r
+ # The default value 0 means C1 state.\r
+ # The value is defined as below.<BR><BR>\r
+ # @Prompt The specified AP target C-state for Mwait.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r
+\r
+ ## Indicates if SMM uses static page table.\r
+ # If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.\r
+ # This flag only impacts X64 build, because SMM always builds static page table for IA32.\r
+ # It could not be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r
+ # It could not be enabled also at the same time with heap guard feature for SMM\r
+ # (PcdHeapGuardPropertyMask in MdeModulePkg).<BR><BR>\r
+ # TRUE - SMM uses static page table for all memory.<BR>\r
+ # FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.<BR>\r
+ # @Prompt Use static page table for all memory in SMM.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable|TRUE|BOOLEAN|0x3213210D\r
+\r
+ ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r
+ # @Prompt AP synchronization timeout value in SMM.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r
+\r
+ ## Indicates the CPU synchronization method used when processing an SMI.\r
+ # 0x00 - Traditional CPU synchronization method.<BR>\r
+ # 0x01 - Relaxed CPU synchronization method.<BR>\r
+ # @Prompt SMM CPU Synchronization Method.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014\r
+\r
+ ## Specifies user's desired settings for enabling/disabling processor features.\r
+ # @Prompt User settings for enabling/disabling processor features.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesUserConfiguration|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000017\r
+\r
+ ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.\r
+ # @Prompt The encoded values for target duty cycle modulation.\r
+ # @ValidRange 0x80000001 | 0 - 15\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A\r
+\r
+ ## Indicates if the current boot is a power-on reset.<BR><BR>\r
+ # TRUE - Current boot is a power-on reset.<BR>\r
+ # FALSE - Current boot is not a power-on reset.<BR>\r
+ # @Prompt Current boot is a power-on reset.\r
+ gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B\r
\r
[PcdsDynamic, PcdsDynamicEx]\r
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
# @ValidList 0x80000001 | 0\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011\r
\r
+ ## Indicates processor feature capabilities, each bit corresponding to a specific feature.\r
+ # @Prompt Processor feature capabilities.\r
+ # @ValidList 0x80000001 | 0\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018\r
+\r
+ ## Specifies actual settings for processor features, each bit corresponding to a specific feature.\r
+ # @Prompt Actual processor feature settings.\r
+ # @ValidList 0x80000001 | 0\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019\r
+\r
+ ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>\r
+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
+ # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
+ # Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>\r
+ # 0x0 - 4K.<BR>\r
+ # 0x1 - 8K.<BR>\r
+ # 0x2 - 16K.<BR>\r
+ # 0x3 - 32K.<BR>\r
+ # 0x4 - 64K.<BR>\r
+ # 0x5 - 128K.<BR>\r
+ # 0x6 - 256K.<BR>\r
+ # 0x7 - 512K.<BR>\r
+ # 0x8 - 1M.<BR>\r
+ # 0x9 - 2M.<BR>\r
+ # 0xA - 4M.<BR>\r
+ # 0xB - 8M.<BR>\r
+ # 0xC - 16M.<BR>\r
+ # 0xD - 32M.<BR>\r
+ # 0xE - 64M.<BR>\r
+ # 0xF - 128M.<BR>\r
+ # @Prompt The memory size used for processor trace if processor trace is enabled.\r
+ # @ValidRange 0x80000001 | 0 - 0xF\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012\r
+\r
+ ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>\r
+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
+ # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
+ # Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>\r
+ # 0 - Single Range output scheme.<BR>\r
+ # 1 - ToPA(Table of physical address) scheme.<BR>\r
+ # @Prompt The processor trace output scheme used when processor trace is enabled.\r
+ # @ValidRange 0x80000001 | 0 - 1\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015\r
+\r
[UserExtensions.TianoCore."ExtraFiles"]\r
UefiCpuPkgExtra.uni\r
projects / mirror_edk2.git / blobdiff