UefiPayloadPkg: Enhance UEFI payload for coreboot and Slim Bootloader

[mirror_edk2.git] / UefiPayloadPkg / Library / PlatformHookLib / PlatformHookLib.c

diff --git a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
new file mode 100644 (file)
index 0000000..72a17dc
--- /dev/null
+++ b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
@@ -0,0 +1,98 @@
+/** @file\r
+  Platform Hook Library instance for UART device.\r
+\r
+  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <Base.h>\r
+#include <Uefi/UefiBaseType.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/PlatformHookLib.h>\r
+#include <Library/BlParseLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+typedef struct {\r
+  UINT16  VendorId;          ///< Vendor ID to match the PCI device.  The value 0xFFFF terminates the list of entries.\r
+  UINT16  DeviceId;          ///< Device ID to match the PCI device\r
+  UINT32  ClockRate;         ///< UART clock rate.  Set to 0 for default clock rate of 1843200 Hz\r
+  UINT64  Offset;            ///< The byte offset into to the BAR\r
+  UINT8   BarIndex;          ///< Which BAR to get the UART base address\r
+  UINT8   RegisterStride;    ///< UART register stride in bytes.  Set to 0 for default register stride of 1 byte.\r
+  UINT16  ReceiveFifoDepth;  ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+  UINT16  TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+  UINT8   Reserved[2];\r
+} PCI_SERIAL_PARAMETER;\r
+\r
+/**\r
+  Performs platform specific initialization required for the CPU to access\r
+  the hardware associated with a SerialPortLib instance.  This function does\r
+  not initialize the serial port hardware itself.  Instead, it initializes\r
+  hardware devices that are required for the CPU to access the serial port\r
+  hardware.  This function may be called more than once.\r
+\r
+  @retval RETURN_SUCCESS       The platform specific initialization succeeded.\r
+  @retval RETURN_DEVICE_ERROR  The platform specific initialization could not be completed.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PlatformHookSerialPortInitialize (\r
+  VOID\r
+  )\r
+{\r
+  RETURN_STATUS         Status;\r
+  UINT32                DeviceVendor;\r
+  PCI_SERIAL_PARAMETER  *SerialParam;\r
+  SERIAL_PORT_INFO      SerialPortInfo;\r
+\r
+  Status = ParseSerialInfo (&SerialPortInfo);\r
+  if (RETURN_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  if (SerialPortInfo.Type == PLD_SERIAL_TYPE_MEMORY_MAPPED) {\r
+    Status = PcdSetBoolS (PcdSerialUseMmio, TRUE);\r
+  } else { //IO\r
+    Status = PcdSetBoolS (PcdSerialUseMmio, FALSE);\r
+  }\r
+  if (RETURN_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+  Status = PcdSet64S (PcdSerialRegisterBase, SerialPortInfo.BaseAddr);\r
+  if (RETURN_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Status = PcdSet32S (PcdSerialRegisterStride, SerialPortInfo.RegWidth);\r
+  if (RETURN_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Status = PcdSet32S (PcdSerialBaudRate, SerialPortInfo.Baud);\r
+  if (RETURN_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Status = PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo.Baud);\r
+  if (RETURN_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Status = PcdSet32S (PcdSerialClockRate, SerialPortInfo.InputHertz);\r
+  if (RETURN_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  if (SerialPortInfo.UartPciAddr >= 0x80000000) {\r
+    DeviceVendor = PciRead32 (SerialPortInfo.UartPciAddr & 0x0ffff000);\r
+    SerialParam  = PcdGetPtr(PcdPciSerialParameters);\r
+    SerialParam->VendorId  = (UINT16)DeviceVendor;\r
+    SerialParam->DeviceId  = DeviceVendor >> 16;\r
+    SerialParam->ClockRate = SerialPortInfo.InputHertz;\r
+    SerialParam->RegisterStride = (UINT8)SerialPortInfo.RegWidth;\r
+  }\r
+\r
+  return RETURN_SUCCESS;\r
+}\r