+++ /dev/null
-/**************************************************************************;\r
-;* *;\r
-;* *;\r
-;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r
-;* Family of Customer Reference Boards. *;\r
-;* *;\r
-;* *;\r
-;* Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved *;\r
-;\r
-; SPDX-License-Identifier: BSD-2-Clause-Patent\r
-;\r
-;* *;\r
-;* *;\r
-;**************************************************************************/\r
-\r
-\r
-\r
-// Define a Global region of ACPI NVS Region that may be used for any\r
-// type of implementation. The starting offset and size will be fixed\r
-// up by the System BIOS during POST. Note that the Size must be a word\r
-// in size to be fixed up correctly.\r
-\r
-OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)\r
-Field(GNVS,AnyAcc,Lock,Preserve)\r
-{\r
- Offset(0), // Miscellaneous Dynamic Registers:\r
- OSYS, 16, // (00) Operating System\r
- , 8, // (02)\r
- , 8, // (03)\r
- , 8, // (04)\r
- , 8, // (05)\r
- , 8, // (06)\r
- , 8, // (07)\r
- , 8, // (08)\r
- , 8, // (09)\r
- , 8, // (10)\r
- P80D, 32, // (11) Port 80 Debug Port Value\r
- LIDS, 8, // (15) Lid State (Lid Open = 1)\r
- , 8, // (16)\r
- , 8, // (17)\r
- Offset(18), // Thermal Policy Registers:\r
- , 8, // (18)\r
- , 8, // (19)\r
- ACTT, 8, // (20) Active Trip Point\r
- PSVT, 8, // (21) Passive Trip Point\r
- TC1V, 8, // (22) Passive Trip Point TC1 Value\r
- TC2V, 8, // (23) Passive Trip Point TC2 Value\r
- TSPV, 8, // (24) Passive Trip Point TSP Value\r
- CRTT, 8, // (25) Critical Trip Point\r
- DTSE, 8, // (26) Digital Thermal Sensor Enable\r
- DTS1, 8, // (27) Digital Thermal Sensor 1 Reading\r
- DTS2, 8, // (28) Digital Thermal Sensor 2 Reading\r
- DTSF, 8, // (29) DTS SMI Function Call\r
- Offset(30), // Battery Support Registers:\r
- , 8, // (30)\r
- , 8, // (31)\r
- , 8, // (32)\r
- , 8, // (33)\r
- , 8, // (34)\r
- , 8, // (35)\r
- , 8, // (36)\r
- Offset(40), // CPU Identification Registers:\r
- APIC, 8, // (40) APIC Enabled by SBIOS (APIC Enabled = 1)\r
- MPEN, 8, // (41) Number of Logical Processors if MP Enabled != 0\r
- , 8, // (42)\r
- , 8, // (43)\r
- , 8, // (44)\r
- , 32, // (45)\r
- Offset(50), // SIO CMOS Configuration Registers:\r
- , 8, // (50)\r
- , 8, // (51)\r
- , 8, // (52)\r
- , 8, // (53)\r
- , 8, // (54)\r
- , 8, // (55)\r
- , 8, // (56)\r
- , 8, // (57)\r
- , 8, // (58)\r
- Offset(60), // Internal Graphics Registers:\r
- , 8, // (60)\r
- , 8, // (61)\r
- CADL, 8, // (62) Current Attached Device List\r
- , 8, // (63)\r
- CSTE, 16, // (64) Current Display State\r
- NSTE, 16, // (66) Next Display State\r
- , 16, // (68)\r
- NDID, 8, // (70) Number of Valid Device IDs\r
- DID1, 32, // (71) Device ID 1\r
- DID2, 32, // (75) Device ID 2\r
- DID3, 32, // (79) Device ID 3\r
- DID4, 32, // (83) Device ID 4\r
- DID5, 32, // (87) Device ID 5\r
- , 32, // (91)\r
- , 8, // (95) Fifth byte of AKSV (mannufacturing mode)\r
- Offset(103), // Backlight Control Registers:\r
- , 8, // (103)\r
- BRTL, 8, // (104) Brightness Level Percentage\r
- Offset(105), // Ambiant Light Sensor Registers:\r
- , 8, // (105)\r
- , 8, // (106)\r
- LLOW, 8, // (107) LUX Low Value\r
- , 8, // (108)\r
- Offset(110), // EMA Registers:\r
- , 8, // (110)\r
- , 16, // (111)\r
- , 16, // (113)\r
- Offset(116), // MEF Registers:\r
- , 8, // (116) MEF Enable\r
- Offset(117), // PCIe Dock:\r
- , 8, // (117)\r
- Offset(120), // TPM Registers:\r
- , 8, // (120)\r
- , 8, // (121)\r
- , 8, // (122)\r
- , 8, // (123)\r
- , 32, // (124)\r
- , 8, // (125)\r
- , 8, // (129)\r
- Offset(130), //\r
- , 56, // (130)\r
- , 56, // (137)\r
- , 8, // (144)\r
- , 56, // (145)\r
- Offset(170), // IGD OpRegion/Software SCI base address\r
- ASLB, 32, // (170) IGD OpRegion base address\r
- Offset(174), // IGD OpRegion/Software SCI shared data\r
- IBTT, 8, // (174) IGD Boot Display Device\r
- IPAT, 8, // (175) IGD Panel Type CMOs option\r
- ITVF, 8, // (176) IGD TV Format CMOS option\r
- ITVM, 8, // (177) IGD TV Minor Format CMOS option\r
- IPSC, 8, // (178) IGD Panel Scaling\r
- IBLC, 8, // (179) IGD BLC Configuration\r
- IBIA, 8, // (180) IGD BIA Configuration\r
- ISSC, 8, // (181) IGD SSC Configuration\r
- I409, 8, // (182) IGD 0409 Modified Settings Flag\r
- I509, 8, // (183) IGD 0509 Modified Settings Flag\r
- I609, 8, // (184) IGD 0609 Modified Settings Flag\r
- I709, 8, // (185) IGD 0709 Modified Settings Flag\r
- IDMM, 8, // (186) IGD DVMT Mode\r
- IDMS, 8, // (187) IGD DVMT Memory Size\r
- IF1E, 8, // (188) IGD Function 1 Enable\r
- HVCO, 8, // (189) HPLL VCO\r
- NXD1, 32, // (190) Next state DID1 for _DGS\r
- NXD2, 32, // (194) Next state DID2 for _DGS\r
- NXD3, 32, // (198) Next state DID3 for _DGS\r
- NXD4, 32, // (202) Next state DID4 for _DGS\r
- NXD5, 32, // (206) Next state DID5 for _DGS\r
- NXD6, 32, // (210) Next state DID6 for _DGS\r
- NXD7, 32, // (214) Next state DID7 for _DGS\r
- NXD8, 32, // (218) Next state DID8 for _DGS\r
- GSMI, 8, // (222) GMCH SMI/SCI mode (0=SCI)\r
- PAVP, 8, // (223) IGD PAVP data\r
- Offset(225),\r
- OSCC, 8, // (225) PCIE OSC Control\r
- NEXP, 8, // (226) Native PCIE Setup Value\r
- Offset(235), // Global Variables\r
- DSEN, 8, // (235) _DOS Display Support Flag.\r
- ECON, 8, // (236) Embedded Controller Availability Flag.\r
- GPIC, 8, // (237) Global IOAPIC/8259 Interrupt Mode Flag.\r
- CTYP, 8, // (238) Global Cooling Type Flag.\r
- L01C, 8, // (239) Global L01 Counter.\r
- VFN0, 8, // (240) Virtual Fan0 Status.\r
- VFN1, 8, // (241) Virtual Fan1 Status.\r
- Offset(256),\r
- NVGA, 32, // (256) NVIG opregion address\r
- NVHA, 32, // (260) NVHM opregion address\r
- AMDA, 32, // (264) AMDA opregion address\r
- DID6, 32, // (268) Device ID 6\r
- DID7, 32, // (272) Device ID 7\r
- DID8, 32, // (276) Device ID 8\r
- Offset(332),\r
- USEL, 8, // (332) UART Selection\r
- PU1E, 8, // (333) PCU UART 1 Enabled\r
- PU2E, 8, // (334) PCU UART 2 Enabled\r
-\r
- LPE0, 32, // (335) LPE Bar0\r
- LPE1, 32, // (339) LPE Bar1\r
- LPE2, 32, // (343) LPE Bar2\r
-\r
- Offset(347),\r
- , 8, // (347)\r
- , 8, // (348)\r
- PFLV, 8, // (349) Platform Flavor\r
-\r
- Offset(351),\r
- ICNF, 8, // (351) ISCT / AOAC Configuration\r
- XHCI, 8, // (352) xHCI controller mode\r
- PMEN, 8, // (353) PMIC enable/disable\r
-\r
- LPEE, 8, // (354) LPE enable/disable\r
- ISPA, 32, // (355) ISP Base Addr\r
- ISPD, 8, // (359) ISP Device Selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3\r
-\r
- offset(360), // ((4+8+6)*4+2)*4=296\r
- //\r
- // Lpss controllers\r
- //\r
- PCIB, 32,\r
- PCIT, 32,\r
- D10A, 32, //DMA1\r
- D10L, 32,\r
- D11A, 32,\r
- D11L, 32,\r
- P10A, 32, // PWM1\r
- P10L, 32,\r
- P11A, 32,\r
- P11L, 32,\r
- P20A, 32, // PWM2\r
- P20L, 32,\r
- P21A, 32,\r
- P21L, 32,\r
- U10A, 32, // UART1\r
- U10L, 32,\r
- U11A, 32,\r
- U11L, 32,\r
- U20A, 32, // UART2\r
- U20L, 32,\r
- U21A, 32,\r
- U21L, 32,\r
- SP0A, 32, // SPI\r
- SP0L, 32,\r
- SP1A, 32,\r
- SP1L, 32,\r
-\r
- D20A, 32, //DMA2\r
- D20L, 32,\r
- D21A, 32,\r
- D21L, 32,\r
- I10A, 32, // I2C1\r
- I10L, 32,\r
- I11A, 32,\r
- I11L, 32,\r
- I20A, 32, // I2C2\r
- I20L, 32,\r
- I21A, 32,\r
- I21L, 32,\r
- I30A, 32, // I2C3\r
- I30L, 32,\r
- I31A, 32,\r
- I31L, 32,\r
- I40A, 32, // I2C4\r
- I40L, 32,\r
- I41A, 32,\r
- I41L, 32,\r
- I50A, 32, // I2C5\r
- I50L, 32,\r
- I51A, 32,\r
- I51L, 32,\r
- I60A, 32, // I2C6\r
- I60L, 32,\r
- I61A, 32,\r
- I61L, 32,\r
- I70A, 32, // I2C7\r
- I70L, 32,\r
- I71A, 32,\r
- I71L, 32,\r
- //\r
- // Scc controllers\r
- //\r
- eM0A, 32, // EMMC\r
- eM0L, 32,\r
- eM1A, 32,\r
- eM1L, 32,\r
- SI0A, 32, // SDIO\r
- SI0L, 32,\r
- SI1A, 32,\r
- SI1L, 32,\r
- SD0A, 32, // SDCard\r
- SD0L, 32,\r
- SD1A, 32,\r
- SD1L, 32,\r
- MH0A, 32, //\r
- MH0L, 32,\r
- MH1A, 32,\r
- MH1L, 32,\r
-\r
- offset(656),\r
- SDRM, 8,\r
- offset(657),\r
- HLPS, 8, //(657) Hide Devices\r
- offset(658),\r
- OSEL, 8, //(658) OS Seletion - Windows/Android\r
-\r
- offset(659), // VLV1 DPTF\r
- SDP1, 8, //(659) An enumerated value corresponding to SKU\r
- DPTE, 8, //(660) DPTF Enable\r
- THM0, 8, //(661) System Thermal 0\r
- THM1, 8, //(662) System Thermal 1\r
- THM2, 8, //(663) System Thermal 2\r
- THM3, 8, //(664) System Thermal 3\r
- THM4, 8, //(665) System Thermal 3\r
- CHGR, 8, //(666) DPTF Changer Device\r
- DDSP, 8, //(667) DPTF Display Device\r
- DSOC, 8, //(668) DPTF SoC device\r
- DPSR, 8, //(669) DPTF Processor device\r
- DPCT, 32, //(670) DPTF Processor participant critical temperature\r
- DPPT, 32, //(674) DPTF Processor participant passive temperature\r
- DGC0, 32, //(678) DPTF Generic sensor0 participant critical temperature\r
- DGP0, 32, //(682) DPTF Generic sensor0 participant passive temperature\r
- DGC1, 32, //(686) DPTF Generic sensor1 participant critical temperature\r
- DGP1, 32, //(690) DPTF Generic sensor1 participant passive temperature\r
- DGC2, 32, //(694) DPTF Generic sensor2 participant critical temperature\r
- DGP2, 32, //(698) DPTF Generic sensor2 participant passive temperature\r
- DGC3, 32, //(702) DPTF Generic sensor3 participant critical temperature\r
- DGP3, 32, //(706) DPTF Generic sensor3 participant passive temperature\r
- DGC4, 32, //(710)DPTF Generic sensor3 participant critical temperature\r
- DGP4, 32, //(714)DPTF Generic sensor3 participant passive temperature\r
- DLPM, 8, //(718) DPTF Current low power mode setting\r
- DSC0, 32, //(719) DPTF Critical threshold0 for SCU\r
- DSC1, 32, //(723) DPTF Critical threshold1 for SCU\r
- DSC2, 32, //(727) DPTF Critical threshold2 for SCU\r
- DSC3, 32, //(731) DPTF Critical threshold3 for SCU\r
- DSC4, 32, //(735) DPTF Critical threshold3 for SCU\r
- DDBG, 8, //(739) DPTF Super Debug option. 0 - Disabled, 1 - Enabled\r
- LPOE, 32, //(740) DPTF LPO Enable\r
- LPPS, 32, //(744) P-State start index\r
- LPST, 32, //(748) Step size\r
- LPPC, 32, //(752) Power control setting\r
- LPPF, 32, //(756) Performance control setting\r
- DPME, 8, //(760) DPTF DPPM enable/disable\r
- BCSL, 8, //(761) Battery charging solution 0-CLV 1-ULPMC\r
- NFCS, 8, //(762) NFCx Select 1: NFC1 2:NFC2\r
- PCIM, 8, //(763) EMMC device 0-ACPI mode, 1-PCI mode\r
- TPMA, 32, //(764)\r
- TPML, 32, //(768)\r
- ITSA, 8, //(772) I2C Touch Screen Address\r
- S0IX, 8, //(773) S0ix status\r
- SDMD, 8, //(774) SDIO Mode\r
- EMVR, 8, //(775) eMMC controller version\r
- BMBD, 32, //(776) BM Bound\r
- FSAS, 8, //(780) FSA Status\r
- BDID, 8, //(781) Board ID\r
- FBID, 8, //(782) FAB ID\r
- OTGM, 8, //(783) OTG mode\r
- STEP, 8, //(784) Stepping ID\r
- WITT, 8, //(785) Enable Test Device connected to I2C for WHCK test.\r
- SOCS, 8, //(786) provide the SoC stepping infomation\r
- AMTE, 8, //(787) Ambient Trip point change\r
- UTS, 8, //(788) Enable Test Device connected to URT for WHCK test.\r
- SCPE, 8, //(789) Allow higher performance on AC/USB - Enable/Disable\r
- Offset(792),\r
- EDPV, 8, //(792) Check for eDP display device\r
- DIDX, 32, //(793) Device ID for eDP device\r
- IOT, 8, //(794) MinnowBoard Max JP1 is configured for MSFT IOT project.\r
- BATT, 8, //(795) The Flag of RTC Battery Prensent.\r
- LPAD, 8, //(796)\r
-}\r
-\r
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