+++ /dev/null
-/**************************************************************************;\r
-;* *;\r
-;* *;\r
-;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r
-;* Family of Customer Reference Boards. *;\r
-;* *;\r
-;* *;\r
-;* Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved *;\r
-;\r
-; SPDX-License-Identifier: BSD-2-Clause-Patent\r
-;\r
-;* *;\r
-;* *;\r
-;**************************************************************************/\r
-\r
-\r
-Scope(\)\r
-{\r
- //\r
- // Define VLV ABASE I/O as an ACPI operating region. The base address\r
- // can be found in Device 31, Registers 40-43h.\r
- //\r
- OperationRegion(PMIO, SystemIo, \PMBS, 0x46)\r
- Field(PMIO, ByteAcc, NoLock, Preserve)\r
- {\r
- , 8,\r
- PWBS, 1, // Power Button Status\r
- Offset(0x20),\r
- , 13,\r
- PMEB, 1, // PME_B0_STS\r
- Offset(0x42), // General Purpose Control\r
- , 1,\r
- GPEC, 1\r
- }\r
- Field(PMIO, ByteAcc, NoLock, WriteAsZeros)\r
- {\r
- Offset(0x20), // GPE0 Status\r
- , 4,\r
- PSCI, 1, // PUNIT SCI Status\r
- SCIS, 1 // GUNIT SCI Status\r
- }\r
-\r
-\r
-\r
- //\r
- // Define a Memory Region that will allow access to the PMC\r
- // Register Block. Note that in the Intel Reference Solution, the PMC\r
- // will get fixed up dynamically during POST.\r
- //\r
- OperationRegion(PMCR, SystemMemory, \PFDR, 0x04)// PMC Function Disable Register\r
- Field(PMCR,DWordAcc,Lock,Preserve)\r
- {\r
- Offset(0x00), // Function Disable Register\r
- L10D, 1, // (0) LPIO1 DMA Disable\r
- L11D, 1, // (1) LPIO1 PWM #1 Disable\r
- L12D, 1, // (2) LPIO1 PWM #2 Disable\r
- L13D, 1, // (3) LPIO1 HS-UART #1 Disable\r
- L14D, 1, // (4) LPIO1 HS-UART #2 Disable\r
- L15D, 1, // (5) LPIO1 SPI Disable\r
- , 2, // (6:7) Reserved\r
- SD1D, 1, // (8) SCC SDIO #1 Disable\r
- SD2D, 1, // (9) SCC SDIO #2 Disable\r
- SD3D, 1, // (10) SCC SDIO #3 Disable\r
- HSID, 1, // (11)\r
- HDAD, 1, // (12) Azalia Disable\r
- LPED, 1, // (13) LPE Disable\r
- OTGD, 1, // (14) USB OTG Disable\r
- , 1, // (15) USH Disable\r
- , 1, // (16)\r
- , 1, // (17)\r
- , 1, // (18) USB Disable\r
- , 1, // (19) SEC Disable\r
- RP1D, 1, // (20) Root Port 0 Disable\r
- RP2D, 1, // (21) Root Port 1 Disable\r
- RP3D, 1, // (22) Root Port 2 Disable\r
- RP4D, 1, // (23) Root Port 3 Disable\r
- L20D, 1, // (24) LPIO2 DMA Disable\r
- L21D, 1, // (25) LPIO2 I2C #1 Disable\r
- L22D, 1, // (26) LPIO2 I2C #2 Disable\r
- L23D, 1, // (27) LPIO2 I2C #3 Disable\r
- L24D, 1, // (28) LPIO2 I2C #4 Disable\r
- L25D, 1, // (29) LPIO2 I2C #5 Disable\r
- L26D, 1, // (30) LPIO2 I2C #6 Disable\r
- L27D, 1 // (31) LPIO2 I2C #7 Disable\r
- }\r
-\r
-\r
- OperationRegion(CLKC, SystemMemory, \PCLK, 0x18)// PMC CLK CTL Registers\r
- Field(CLKC,DWordAcc,Lock,Preserve)\r
- {\r
- Offset(0x00), // PLT_CLK_CTL_0\r
- CKC0, 2,\r
- CKF0, 1,\r
- , 29,\r
- Offset(0x04), // PLT_CLK_CTL_1\r
- CKC1, 2,\r
- CKF1, 1,\r
- , 29,\r
- Offset(0x08), // PLT_CLK_CTL_2\r
- CKC2, 2,\r
- CKF2, 1,\r
- , 29,\r
- Offset(0x0C), // PLT_CLK_CTL_3\r
- CKC3, 2,\r
- CKF3, 1,\r
- , 29,\r
- Offset(0x10), // PLT_CLK_CTL_4\r
- CKC4, 2,\r
- CKF4, 1,\r
- , 29,\r
- Offset(0x14), // PLT_CLK_CTL_5\r
- CKC5, 2,\r
- CKF5, 1,\r
- , 29,\r
- }\r
-} //end Scope(\)\r
-\r
-scope (\_SB)\r
-{\r
- Device(LPEA)\r
- {\r
- Name (_ADR, 0)\r
- Name (_HID, "80860F28")\r
- Name (_CID, "80860F28")\r
- //Name (_CLS, Package (3) {0x04, 0x01, 0x00})\r
- Name (_DDN, "Intel(R) Low Power Audio Controller - 80860F28")\r
- Name (_SUB, "80867270")\r
- Name (_UID, 1)\r
- Name (_DEP, Package() {\_SB.I2C2.RTEK})\r
- Name(_PR0,Package() {PLPE})\r
-\r
- Method (_STA, 0x0, NotSerialized)\r
- {\r
- If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 0)))\r
- {\r
- If(LEqual(LPAD, 1))\r
- {\r
- Return (0xF)\r
- }\r
- }\r
- Return (0x0)\r
- }\r
-\r
- Method (_DIS, 0x0, NotSerialized)\r
- {\r
- //Add a dummy disable function\r
- }\r
-\r
- Name (RBUF, ResourceTemplate ()\r
- {\r
- Memory32Fixed (ReadWrite, 0xFE400000, 0x00200000, BAR0) // MMIO 1 - LPE MMIO\r
- Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space\r
- Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post\r
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}\r
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {25}\r
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {26}\r
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {27}\r
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {28}\r
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}\r
- GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO2") {28} // Audio jack interrupt\r
- }\r
- )\r
-\r
- Method (_CRS, 0x0, NotSerialized)\r
- {\r
- CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
- Store(LPE0, B0BA)\r
- CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)\r
- Store(LPE1, B1BA)\r
- CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)\r
- Store(LPE2, B2BA)\r
- Return (RBUF)\r
- }\r
-\r
- OperationRegion (KEYS, SystemMemory, LPE1, 0x100)\r
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
- {\r
- Offset (0x84),\r
- PSAT, 32\r
- }\r
-\r
- PowerResource(PLPE, 0, 0) // Power Resource for LPEA\r
- {\r
- Method (_STA)\r
- {\r
- Return (1) // Power Resource is always available.\r
- }\r
-\r
- Method (_ON)\r
- {\r
- And(PSAT, 0xfffffffC, PSAT)\r
- OR(PSAT, 0X00000000, PSAT)\r
- }\r
-\r
- Method (_OFF)\r
- {\r
- OR(PSAT, 0x00000003, PSAT)\r
- OR(PSAT, 0X00000000, PSAT)\r
- }\r
- } // End PLPE\r
- } // End "Low Power Engine Audio"\r
-\r
- Device(LPA2)\r
- {\r
- Name (_ADR, 0)\r
- Name (_HID, "LPE0F28") // _HID: Hardware ID\r
- Name (_CID, "LPE0F28") // _CID: Compatible ID\r
- Name (_DDN, "Intel(R) SST Audio - LPE0F28") // _DDN: DOS Device Name\r
- Name (_SUB, "80867270")\r
- Name (_UID, 1)\r
- Name (_DEP, Package() {\_SB.I2C2.RTEK})\r
- Name(_PR0,Package() {PLPE})\r
-\r
- Method (_STA, 0x0, NotSerialized)\r
- {\r
- If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 1)))\r
- {\r
- If(LEqual(LPAD, 1))\r
- {\r
- Return (0xF)\r
- }\r
- }\r
- Return (0x0)\r
- }\r
-\r
- Method (_DIS, 0x0, NotSerialized)\r
- {\r
- //Add a dummy disable function\r
- }\r
-\r
- Name (RBUF, ResourceTemplate ()\r
- {\r
- Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post\r
- Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00000100, SHIM)\r
- Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, MBOX)\r
- Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00014000, IRAM)\r
- Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00028000, DRAM)\r
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}\r
- Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space\r
- }\r
- )\r
-\r
- Method (_CRS, 0x0, NotSerialized)\r
- {\r
- CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)\r
- Add(LPE0, 0x140000, SHBA)\r
- CreateDwordField(^RBUF, ^MBOX._BAS, MBBA)\r
- Add(LPE0, 0x144000, MBBA)\r
- CreateDwordField(^RBUF, ^IRAM._BAS, IRBA)\r
- Add(LPE0, 0xC0000, IRBA)\r
- CreateDwordField(^RBUF, ^DRAM._BAS, DRBA)\r
- Add(LPE0, 0x100000, DRBA)\r
- CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)\r
- Store(LPE1, B1BA)\r
- CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)\r
- Store(LPE2, B2BA)\r
- Return (RBUF)\r
- }\r
-\r
- OperationRegion (KEYS, SystemMemory, LPE1, 0x100)\r
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
- {\r
- Offset (0x84),\r
- PSAT, 32\r
- }\r
-\r
- PowerResource(PLPE, 0, 0) // Power Resource for LPEA\r
- {\r
- Method (_STA)\r
- {\r
- Return (1) // Power Resource is always available.\r
- }\r
-\r
- Method (_ON)\r
- {\r
- And(PSAT, 0xfffffffC, PSAT)\r
- OR(PSAT, 0X00000000, PSAT)\r
- }\r
-\r
- Method (_OFF)\r
- {\r
- OR(PSAT, 0x00000003, PSAT)\r
- OR(PSAT, 0X00000000, PSAT)\r
- }\r
- } // End PLPE\r
-\r
- Device (ADMA)\r
- {\r
- Name (_ADR, Zero) // _ADR: Address\r
- Name (_HID, "DMA0F28") // _HID: Hardware ID\r
- Name (_CID, "DMA0F28") // _CID: Compatible ID\r
- Name (_DDN, "Intel(R) Audio DMA0 - DMA0F28") // _DDN: DOS Device Name\r
- Name (_UID, One) // _UID: Unique ID\r
- Name (RBUF, ResourceTemplate ()\r
- {\r
- Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, DMA0) // LPE BASE + LPE DMA0 offset\r
- Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, SHIM) // LPE BASE + LPE SHIM offset\r
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}\r
- })\r
-\r
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings\r
- {\r
- CreateDwordField(^RBUF, ^DMA0._BAS, D0BA)\r
- Add(LPE0, 0x98000, D0BA)\r
- CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)\r
- Add(LPE0, 0x140000, SHBA)\r
- Return (RBUF)\r
- }\r
- }\r
- } // End "Low Power Engine Audio" for Android\r
-}\r
-\r
-scope (\_SB.PCI0)\r
-{\r
-\r
- //\r
- // Serial ATA Host Controller - Device 19, Function 0\r
- //\r
-\r
- Device(SATA)\r
- {\r
- Name(_ADR,0x00130000)\r
- //\r
- // SATA Methods pulled in via SSDT.\r
- //\r
-\r
- OperationRegion(SATR, PCI_Config, 0x74,0x4)\r
- Field(SATR,WordAcc,NoLock,Preserve)\r
- {\r
- Offset(0x00), // 0x74, PMCR\r
- , 8,\r
- PMEE, 1, //PME_EN\r
- , 6,\r
- PMES, 1 //PME_STS\r
- }\r
-\r
- Method (_STA, 0x0, NotSerialized)\r
- {\r
- Return(0xf)\r
- }\r
-\r
- Method(_DSW, 3)\r
- {\r
- } // End _DSW\r
- }\r
-\r
- //\r
- // For eMMC 4.41 PCI mode in order to present non-removable device under Windows environment\r
- //\r
- Device(EM41)\r
- {\r
- Name(_ADR,0x00100000)\r
- OperationRegion(SDIO, PCI_Config, 0x84,0x4)\r
- Field(SDIO,WordAcc,NoLock,Preserve)\r
- {\r
- Offset(0x00), // 0x84, PMCR\r
- , 8,\r
- PMEE, 1, //PME_EN\r
- , 6,\r
- PMES, 1 //PME_STS\r
- }\r
-\r
- Method (_STA, 0x0, NotSerialized)\r
- {\r
- If (LAnd(LEqual(PCIM, 1), LEqual(SD1D, 0)))\r
- {\r
- Return(0xF)\r
- }\r
- Else\r
- {\r
- Return(0x0)\r
- }\r
- }\r
-\r
- Method(_DSW, 3)\r
- {\r
- } // End _DSW\r
-\r
- Device (CARD)\r
- {\r
- Name (_ADR, 0x00000008)\r
- Method(_RMV, 0x0, NotSerialized)\r
- {\r
- Return (0)\r
- } // End _DSW\r
- }\r
- }\r
-\r
- //\r
- // For eMMC 4.5 PCI mode in order to present non-removable device under Windows environment\r
- //\r
- Device(EM45)\r
- {\r
- Name(_ADR,0x00170000)\r
- OperationRegion(SDIO, PCI_Config, 0x84,0x4)\r
- Field(SDIO,WordAcc,NoLock,Preserve)\r
- {\r
- Offset(0x00), // 0x84, PMCR\r
- , 8,\r
- PMEE, 1, //PME_EN\r
- , 6,\r
- PMES, 1 //PME_STS\r
- }\r
-\r
- Method (_STA, 0x0, NotSerialized)\r
- {\r
- If (LAnd(LEqual(PCIM, 1), LEqual(HSID, 0)))\r
- {\r
- Return(0xF)\r
- }\r
- Else\r
- {\r
- Return(0x0)\r
- }\r
- }\r
-\r
- Method(_DSW, 3)\r
- {\r
- } // End _DSW\r
-\r
- Device (CARD)\r
- {\r
- Name (_ADR, 0x00000008)\r
- Method(_RMV, 0x0, NotSerialized)\r
- {\r
- Return (0)\r
- } // End _DSW\r
- }\r
- }\r
- //\r
- // For SD Host Controller (Bus 0x00 : Dev 0x12 : Func 0x00) PCI mode in order to present non-removable device under Windows environment\r
- //\r
- Device(SD12)\r
- {\r
- Name(_ADR,0x00120000)\r
-\r
- Method (_STA, 0x0, NotSerialized)\r
- {\r
- //\r
- // PCIM>> 0:ACPI mode 1:PCI mode\r
- //\r
- If (LEqual(PCIM, 0)) {\r
- Return (0x0)\r
- }\r
-\r
- //\r
- // If device is disabled.\r
- //\r
- If (LEqual(SD3D, 1))\r
- {\r
- Return (0x0)\r
- }\r
-\r
- Return (0xF)\r
- }\r
-\r
- Device (CARD)\r
- {\r
- Name (_ADR, 0x00000008)\r
- Method(_RMV, 0x0, NotSerialized)\r
- {\r
- // SDRM = 0 non-removable;\r
- If (LEqual(SDRM, 0))\r
- {\r
- Return (0)\r
- }\r
-\r
- Return (1)\r
- }\r
- }\r
- }\r
-\r
- // xHCI Controller - Device 20, Function 0\r
- include("PchXhci.asl")\r
-\r
- //\r
- // High Definition Audio Controller - Device 27, Function 0\r
- //\r
- Device(HDEF)\r
- {\r
- Name(_ADR, 0x001B0000)\r
- include("PchAudio.asl")\r
-\r
- Method (_STA, 0x0, NotSerialized)\r
- {\r
- If (LEqual(HDAD, 0))\r
- {\r
- Return(0xf)\r
- }\r
- Return(0x0)\r
- }\r
-\r
- Method(_DSW, 3)\r
- {\r
- } // End _DSW\r
- } // end "High Definition Audio Controller"\r
-\r
-\r
-\r
- //\r
- // PCIE Root Port #1\r
- //\r
- Device(RP01)\r
- {\r
- Name(_ADR, 0x001C0000)\r
- include("PchPcie.asl")\r
- Name(_PRW, Package() {9, 4})\r
-\r
- Method(_PRT,0)\r
- {\r
- If(PICM) { Return(AR04) }// APIC mode\r
- Return (PR04) // PIC Mode\r
- } // end _PRT\r
- } // end "PCIE Root Port #1"\r
-\r
- //\r
- // PCIE Root Port #2\r
- //\r
- Device(RP02)\r
- {\r
- Name(_ADR, 0x001C0001)\r
- include("PchPcie.asl")\r
- Name(_PRW, Package() {9, 4})\r
-\r
- Method(_PRT,0)\r
- {\r
- If(PICM) { Return(AR05) }// APIC mode\r
- Return (PR05) // PIC Mode\r
- } // end _PRT\r
-\r
- } // end "PCIE Root Port #2"\r
-\r
- //\r
- // PCIE Root Port #3\r
- //\r
- Device(RP03)\r
- {\r
- Name(_ADR, 0x001C0002)\r
- include("PchPcie.asl")\r
- Name(_PRW, Package() {9, 4})\r
- Method(_PRT,0)\r
- {\r
- If(PICM) { Return(AR06) }// APIC mode\r
- Return (PR06) // PIC Mode\r
- } // end _PRT\r
-\r
- } // end "PCIE Root Port #3"\r
-\r
- //\r
- // PCIE Root Port #4\r
- //\r
- Device(RP04)\r
- {\r
- Name(_ADR, 0x001C0003)\r
- include("PchPcie.asl")\r
- Name(_PRW, Package() {9, 4})\r
- Method(_PRT,0)\r
- {\r
- If(PICM) { Return(AR07) }// APIC mode\r
- Return (PR07) // PIC Mode\r
- } // end _PRT\r
-\r
- } // end "PCIE Root Port #4"\r
-\r
-\r
- Scope(\_SB)\r
- {\r
- //\r
- // Dummy power resource for USB D3 cold support\r
- //\r
- PowerResource(USBC, 0, 0)\r
- {\r
- Method(_STA) { Return (0xF) }\r
- Method(_ON) {}\r
- Method(_OFF) {}\r
- }\r
- }\r
- //\r
- // EHCI Controller - Device 29, Function 0\r
- //\r
- Device(EHC1)\r
- {\r
- Name(_ADR, 0x001D0000)\r
- Name(_DEP, Package(0x1)\r
- {\r
- PEPD\r
- })\r
- include("PchEhci.asl")\r
- Name(_PRW, Package() {0x0D, 4})\r
-\r
- OperationRegion(USBR, PCI_Config, 0x54,0x4)\r
- Field(USBR,WordAcc,NoLock,Preserve)\r
- {\r
- Offset(0x00), // 0x54, PMCR\r
- , 8,\r
- PMEE, 1, //PME_EN\r
- , 6,\r
- PMES, 1 //PME_STS\r
- }\r
-\r
- Method (_STA, 0x0, NotSerialized)\r
- {\r
- If(LEqual(XHCI, 0)) //XHCI is not present. It means EHCI is there\r
- {\r
- Return (0xF)\r
- } Else\r
- {\r
- Return (0x0)\r
- }\r
- }\r
-\r
- Method (_RMV, 0, NotSerialized)\r
- {\r
- Return (0x0)\r
- }\r
- //\r
- // Create a dummy PR3 method to indicate to the PCI driver\r
- // that the device is capable of D3 cold\r
- //\r
- Method(_PR3, 0x0, NotSerialized)\r
- {\r
- return (Package() {\_SB.USBC})\r
- }\r
-\r
- } // end "EHCI Controller"\r
-\r
- //\r
- // SMBus Controller - Device 31, Function 3\r
- //\r
- Device(SBUS)\r
- {\r
- Name(_ADR,0x001F0003)\r
- Include("PchSmb.asl")\r
- }\r
-\r
- Device(SEC0)\r
- {\r
- Name (_ADR, 0x001a0000) // Device 0x1a, Function 0\r
- Name(_DEP, Package(0x1)\r
- {\r
- PEPD\r
- })\r
-\r
-\r
- OperationRegion (PMEB, PCI_Config, 0x84, 0x04) //PMECTRLSTATUS\r
- Field (PMEB, WordAcc, NoLock, Preserve)\r
- {\r
- , 8,\r
- PMEE, 1, //bit8 PMEENABLE\r
- , 6,\r
- PMES, 1 //bit15 PMESTATUS\r
- }\r
-\r
- // Arg0 -- integer that contains the device wake capability control (0-disable 1- enable)\r
- // Arg1 -- integer that contains target system state (0-4)\r
- // Arg2 -- integer that contains the target device state\r
- Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake\r
- {\r
- }\r
-\r
- Method (_CRS, 0, NotSerialized)\r
- {\r
- Name (RBUF, ResourceTemplate ()\r
- {\r
- Memory32Fixed (ReadWrite, 0x1e000000, 0x2000000)\r
- })\r
-\r
- If (LEqual(PAVP, 2))\r
- {\r
- Return (RBUF)\r
- }\r
- Return (ResourceTemplate() {})\r
- }\r
-\r
- Method (_STA)\r
- {\r
- If (LNotEqual(PAVP, 0))\r
- {\r
- Return (0xF)\r
- }\r
- Return (0x0)\r
- }\r
- } // Device(SEC0)\r
-\r
-} // End scope (\_SB.PCI0)\r
-\r
projects / mirror_edk2.git / blobdiff