+++ /dev/null
-/**************************************************************************;\r
-;* *;\r
-;* *;\r
-;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *;\r
-;* Family of Customer Reference Boards. *;\r
-;* *;\r
-;* *;\r
-;* Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved *;\r
-;\r
-; SPDX-License-Identifier: BSD-2-Clause-Patent\r
-;\r
-;* *;\r
-;* *;\r
-;**************************************************************************/\r
-\r
-Scope(\_SB)\r
-{\r
-//RTC\r
- Device(RTC) // RTC\r
- {\r
- Name(_HID,EISAID("PNP0B00"))\r
-\r
- Name(_CRS,ResourceTemplate()\r
- {\r
- IO(Decode16,0x70,0x70,0x01,0x08)\r
- })\r
-\r
- Method(_STA,0,Serialized) {\r
-\r
- //\r
- // Report RTC Battery is Prensent or Not Present.\r
- //\r
- If (LEqual(BATT, 1)) {\r
- Return (0xF)\r
- }\r
- Return (0x0)\r
- }\r
- }\r
-//RTC\r
-\r
- Device(HPET) // High Performance Event Timer\r
- {\r
- Name (_HID, EisaId ("PNP0103"))\r
- Name (_UID, 0x00)\r
- Method (_STA, 0, NotSerialized)\r
- {\r
- Return (0x0F)\r
- }\r
-\r
- Method (_CRS, 0, Serialized)\r
- {\r
- Name (RBUF, ResourceTemplate ()\r
- {\r
- Memory32Fixed (ReadWrite,\r
- 0xFED00000, // Address Base\r
- 0x00000400, // Address Length\r
- )\r
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )\r
- {\r
- 0x00000008, //0xB HPET-2\r
- }\r
- })\r
- Return (RBUF)\r
- }\r
- }\r
-//HPET\r
-\r
- Name(PR00, Package()\r
- {\r
-// SD Host #0 - eMMC\r
- Package() {0x0010FFFF, 0, LNKA, 0 },\r
-// SD Host #1 - SDIO\r
- Package() {0x0011FFFF, 0, LNKB, 0 },\r
-// SD Host #2 - SD Card\r
- Package() {0x0012FFFF, 0, LNKC, 0 },\r
-// SATA Controller\r
- Package() {0x0013FFFF, 0, LNKD, 0 },\r
-// xHCI Host\r
- Package() {0x0014FFFF, 0, LNKE, 0 },\r
-// Low Power Audio Engine\r
- Package() {0x0015FFFF, 0, LNKF, 0 },\r
-// USB OTG\r
- Package() {0x0016FFFF, 0, LNKG, 0 },\r
-// MIPI-HSI/eMMC4.5\r
- Package() {0x0017FFFF, 0, LNKH, 0 },\r
-// LPSS2 DMA\r
-// LPSS2 I2C #4\r
- Package() {0x0018FFFF, 0, LNKB, 0 },\r
-// LPSS2 I2C #1\r
-// LPSS2 I2C #5\r
- Package() {0x0018FFFF, 2, LNKD, 0 },\r
-// LPSS2 I2C #2\r
-// LPSS2 I2C #6\r
- Package() {0x0018FFFF, 3, LNKC, 0 },\r
-// LPSS2 I2C #3\r
-// LPSS2 I2C #7\r
- Package() {0x0018FFFF, 1, LNKA, 0 },\r
-// SeC\r
- Package() {0x001AFFFF, 0, LNKF, 0 },\r
-//\r
-// High Definition Audio Controller\r
- Package() {0x001BFFFF, 0, LNKG, 0 },\r
-//\r
-// EHCI Controller\r
- Package() {0x001DFFFF, 0, LNKH, 0 },\r
-// LPSS DMA\r
- Package() {0x001EFFFF, 0, LNKD, 0 },\r
-// LPSS I2C #0\r
- Package() {0x001EFFFF, 3, LNKA, 0 },\r
-// LPSS I2C #1\r
- Package() {0x001EFFFF, 1, LNKB, 0 },\r
-// LPSS PCM\r
- Package() {0x001EFFFF, 2, LNKC, 0 },\r
-// LPSS I2S\r
-// LPSS HS-UART #0\r
-// LPSS HS-UART #1\r
-// LPSS SPI\r
-// LPC Bridge\r
-//\r
-// SMBus Controller\r
- Package() {0x001FFFFF, 1, LNKC, 0 },\r
-//\r
-// PCIE Root Port #1\r
- Package() {0x001CFFFF, 0, LNKA, 0 },\r
-// PCIE Root Port #2\r
- Package() {0x001CFFFF, 1, LNKB, 0 },\r
-// PCIE Root Port #3\r
- Package() {0x001CFFFF, 2, LNKC, 0 },\r
-// PCIE Root Port #4\r
- Package() {0x001CFFFF, 3, LNKD, 0 },\r
-\r
-// Host Bridge\r
-// Mobile IGFX\r
- Package() {0x0002FFFF, 0, LNKA, 0 },\r
- })\r
-\r
- Name(AR00, Package()\r
- {\r
-// SD Host #0 - eMMC\r
- Package() {0x0010FFFF, 0, 0, 16 },\r
-// SD Host #1 - SDIO\r
- Package() {0x0011FFFF, 0, 0, 17 },\r
-// SD Host #2 - SD Card\r
- Package() {0x0012FFFF, 0, 0, 18 },\r
-// SATA Controller\r
- Package() {0x0013FFFF, 0, 0, 19 },\r
-// xHCI Host\r
- Package() {0x0014FFFF, 0, 0, 20 },\r
-// Low Power Audio Engine\r
- Package() {0x0015FFFF, 0, 0, 21 },\r
-// USB OTG\r
- Package() {0x0016FFFF, 0, 0, 22 },\r
-//\r
-// MIPI-HSI\r
- Package() {0x0017FFFF, 0, 0, 23 },\r
-//\r
-// LPSS2 DMA\r
-// LPSS2 I2C #4\r
- Package() {0x0018FFFF, 0, 0, 17 },\r
-// LPSS2 I2C #1\r
-// LPSS2 I2C #5\r
- Package() {0x0018FFFF, 2, 0, 19 },\r
-// LPSS2 I2C #2\r
-// LPSS2 I2C #6\r
- Package() {0x0018FFFF, 3, 0, 18 },\r
-// LPSS2 I2C #3\r
-// LPSS2 I2C #7\r
- Package() {0x0018FFFF, 1, 0, 16 },\r
-\r
-// SeC\r
- Package() {0x001AFFFF, 0, 0, 21 },\r
-//\r
-// High Definition Audio Controller\r
- Package() {0x001BFFFF, 0, 0, 22 },\r
-//\r
-// EHCI Controller\r
- Package() {0x001DFFFF, 0, 0, 23 },\r
-// LPSS DMA\r
- Package() {0x001EFFFF, 0, 0, 19 },\r
-// LPSS I2C #0\r
- Package() {0x001EFFFF, 3, 0, 16 },\r
-// LPSS I2C #1\r
- Package() {0x001EFFFF, 1, 0, 17 },\r
-// LPSS PCM\r
- Package() {0x001EFFFF, 2, 0, 18 },\r
-// LPSS I2S\r
-// LPSS HS-UART #0\r
-// LPSS HS-UART #1\r
-// LPSS SPI\r
-// LPC Bridge\r
-//\r
-// SMBus Controller\r
- Package() {0x001FFFFF, 1, 0, 18 },\r
-//\r
-// PCIE Root Port #1\r
- Package() {0x001CFFFF, 0, 0, 16 },\r
-// PCIE Root Port #2\r
- Package() {0x001CFFFF, 1, 0, 17 },\r
-// PCIE Root Port #3\r
- Package() {0x001CFFFF, 2, 0, 18 },\r
-// PCIE Root Port #4\r
- Package() {0x001CFFFF, 3, 0, 19 },\r
-// Host Bridge\r
-// Mobile IGFX\r
- Package() {0x0002FFFF, 0, 0, 16 },\r
- })\r
-\r
- Name(PR04, Package()\r
- {\r
-// PCIE Port #1 Slot\r
- Package() {0x0000FFFF, 0, LNKA, 0 },\r
- Package() {0x0000FFFF, 1, LNKB, 0 },\r
- Package() {0x0000FFFF, 2, LNKC, 0 },\r
- Package() {0x0000FFFF, 3, LNKD, 0 },\r
- })\r
-\r
- Name(AR04, Package()\r
- {\r
-// PCIE Port #1 Slot\r
- Package() {0x0000FFFF, 0, 0, 16 },\r
- Package() {0x0000FFFF, 1, 0, 17 },\r
- Package() {0x0000FFFF, 2, 0, 18 },\r
- Package() {0x0000FFFF, 3, 0, 19 },\r
- })\r
-\r
- Name(PR05, Package()\r
- {\r
-// PCIE Port #2 Slot\r
- Package() {0x0000FFFF, 0, LNKB, 0 },\r
- Package() {0x0000FFFF, 1, LNKC, 0 },\r
- Package() {0x0000FFFF, 2, LNKD, 0 },\r
- Package() {0x0000FFFF, 3, LNKA, 0 },\r
- })\r
-\r
- Name(AR05, Package()\r
- {\r
-// PCIE Port #2 Slot\r
- Package() {0x0000FFFF, 0, 0, 17 },\r
- Package() {0x0000FFFF, 1, 0, 18 },\r
- Package() {0x0000FFFF, 2, 0, 19 },\r
- Package() {0x0000FFFF, 3, 0, 16 },\r
- })\r
-\r
- Name(PR06, Package()\r
- {\r
-// PCIE Port #3 Slot\r
- Package() {0x0000FFFF, 0, LNKC, 0 },\r
- Package() {0x0000FFFF, 1, LNKD, 0 },\r
- Package() {0x0000FFFF, 2, LNKA, 0 },\r
- Package() {0x0000FFFF, 3, LNKB, 0 },\r
- })\r
-\r
- Name(AR06, Package()\r
- {\r
-// PCIE Port #3 Slot\r
- Package() {0x0000FFFF, 0, 0, 18 },\r
- Package() {0x0000FFFF, 1, 0, 19 },\r
- Package() {0x0000FFFF, 2, 0, 16 },\r
- Package() {0x0000FFFF, 3, 0, 17 },\r
- })\r
-\r
- Name(PR07, Package()\r
- {\r
-// PCIE Port #4 Slot\r
- Package() {0x0000FFFF, 0, LNKD, 0 },\r
- Package() {0x0000FFFF, 1, LNKA, 0 },\r
- Package() {0x0000FFFF, 2, LNKB, 0 },\r
- Package() {0x0000FFFF, 3, LNKC, 0 },\r
- })\r
-\r
- Name(AR07, Package()\r
- {\r
-// PCIE Port #4 Slot\r
- Package() {0x0000FFFF, 0, 0, 19 },\r
- Package() {0x0000FFFF, 1, 0, 16 },\r
- Package() {0x0000FFFF, 2, 0, 17 },\r
- Package() {0x0000FFFF, 3, 0, 18 },\r
- })\r
-\r
- Name(PR01, Package()\r
- {\r
-// PCI slot 1\r
- Package() {0x0000FFFF, 0, LNKF, 0 },\r
- Package() {0x0000FFFF, 1, LNKG, 0 },\r
- Package() {0x0000FFFF, 2, LNKH, 0 },\r
- Package() {0x0000FFFF, 3, LNKE, 0 },\r
-// PCI slot 2\r
- Package() {0x0001FFFF, 0, LNKG, 0 },\r
- Package() {0x0001FFFF, 1, LNKF, 0 },\r
- Package() {0x0001FFFF, 2, LNKE, 0 },\r
- Package() {0x0001FFFF, 3, LNKH, 0 },\r
-// PCI slot 3\r
- Package() {0x0002FFFF, 0, LNKC, 0 },\r
- Package() {0x0002FFFF, 1, LNKD, 0 },\r
- Package() {0x0002FFFF, 2, LNKB, 0 },\r
- Package() {0x0002FFFF, 3, LNKA, 0 },\r
-// PCI slot 4\r
- Package() {0x0003FFFF, 0, LNKD, 0 },\r
- Package() {0x0003FFFF, 1, LNKC, 0 },\r
- Package() {0x0003FFFF, 2, LNKF, 0 },\r
- Package() {0x0003FFFF, 3, LNKG, 0 },\r
- })\r
-\r
- Name(AR01, Package()\r
- {\r
-// PCI slot 1\r
- Package() {0x0000FFFF, 0, 0, 21 },\r
- Package() {0x0000FFFF, 1, 0, 22 },\r
- Package() {0x0000FFFF, 2, 0, 23 },\r
- Package() {0x0000FFFF, 3, 0, 20 },\r
-// PCI slot 2\r
- Package() {0x0001FFFF, 0, 0, 22 },\r
- Package() {0x0001FFFF, 1, 0, 21 },\r
- Package() {0x0001FFFF, 2, 0, 20 },\r
- Package() {0x0001FFFF, 3, 0, 23 },\r
-// PCI slot 3\r
- Package() {0x0002FFFF, 0, 0, 18 },\r
- Package() {0x0002FFFF, 1, 0, 19 },\r
- Package() {0x0002FFFF, 2, 0, 17 },\r
- Package() {0x0002FFFF, 3, 0, 16 },\r
-// PCI slot 4\r
- Package() {0x0003FFFF, 0, 0, 19 },\r
- Package() {0x0003FFFF, 1, 0, 18 },\r
- Package() {0x0003FFFF, 2, 0, 21 },\r
- Package() {0x0003FFFF, 3, 0, 22 },\r
- })\r
-//---------------------------------------------------------------------------\r
-// List of IRQ resource buffers compatible with _PRS return format.\r
-//---------------------------------------------------------------------------\r
-// Naming legend:\r
-// RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.\r
-// Note. PRSy name is generated if IRQ Link name starts from "LNK".\r
-// HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.\r
-//---------------------------------------------------------------------------\r
- Name(PRSA, ResourceTemplate() // Link name: LNKA\r
- {\r
- IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}\r
- })\r
- Alias(PRSA,PRSB) // Link name: LNKB\r
- Alias(PRSA,PRSC) // Link name: LNKC\r
- Alias(PRSA,PRSD) // Link name: LNKD\r
- Alias(PRSA,PRSE) // Link name: LNKE\r
- Alias(PRSA,PRSF) // Link name: LNKF\r
- Alias(PRSA,PRSG) // Link name: LNKG\r
- Alias(PRSA,PRSH) // Link name: LNKH\r
-//---------------------------------------------------------------------------\r
-// Begin PCI tree object scope\r
-//---------------------------------------------------------------------------\r
-\r
- Device(PCI0) // PCI Bridge "Host Bridge"\r
- {\r
- Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy\r
- Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID\r
- Name(_ADR, 0x00000000)\r
- Method(^BN00, 0) { return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope\r
- Method(_BBN, 0) { return(BN00()) } // Bus number, optional for the Root PCI Bus\r
- Name(_UID, 0x0000) // Unique Bus ID, optional\r
- Name(_DEP, Package(0x1)\r
- {\r
- PEPD\r
- })\r
-\r
- Method(_PRT,0)\r
- {\r
- If(PICM) {Return(AR00)} // APIC mode\r
- Return (PR00) // PIC Mode\r
- } // end _PRT\r
-\r
- include("HOST_BUS.ASL")\r
- Device(LPCB) // LPC Bridge\r
- {\r
- Name(_ADR, 0x001F0000)\r
- include("LpcB.asl")\r
- } // end "LPC Bridge"\r
-\r
- } // end PCI0 Bridge "Host Bridge"\r
-} // end _SB scope\r
projects / mirror_edk2.git / blobdiff