--- /dev/null
+/*-----------------------------------------------------------------------------\r
+\r
+\r
+ Intel Silvermont Processor Power Management BIOS Reference Code\r
+\r
+ Copyright (c) 2006 - 2014, Intel Corporation\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+ Filename: CPUPM.ASL\r
+\r
+ Revision: Refer to Readme\r
+\r
+ Date: Refer to Readme\r
+-------------------------------------------------------------------------------\r
+\r
+ This Processor Power Management BIOS Source Code is furnished under license\r
+ and may only be used or copied in accordance with the terms of the license.\r
+ The information in this document is furnished for informational use only, is\r
+ subject to change without notice, and should not be construed as a commitment\r
+ by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
+ for any errors or inaccuracies that may appear in this document or any\r
+ software that may be provided in association with this document.\r
+\r
+ Except as permitted by such license, no part of this document may be\r
+ reproduced, stored in a retrieval system, or transmitted in any form or by\r
+ any means without the express written consent of Intel Corporation.\r
+\r
+ WARNING: You are authorized and licensed to install and use this BIOS code\r
+ ONLY on an IST PC. This utility may damage any system that does not\r
+ meet these requirements.\r
+\r
+ An IST PC is a computer which\r
+ (1) Is capable of seamlessly and automatically transitioning among\r
+ multiple performance states (potentially operating at different\r
+ efficiency ratings) based upon power source changes, END user\r
+ preference, processor performance demand, and thermal conditions; and\r
+ (2) Includes an Intel Pentium II processors, Intel Pentium III\r
+ processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
+ Processor-M, Intel Pentium M Processor, or any other future Intel\r
+ processors that incorporates the capability to transition between\r
+ different performance states by altering some, or any combination of,\r
+ the following processor attributes: core voltage, core frequency, bus\r
+ frequency, number of processor cores available, or any other attribute\r
+ that changes the efficiency (instructions/unit time-power) at which the\r
+ processor operates.\r
+-------------------------------------------------------------------------------\r
+\r
+NOTES:\r
+ (1) <TODO> - Except for the SSDT package, the objects in this ASL code\r
+ may be moved to the DSDT. It is kept separate in this reference package\r
+ for ease of distribution only.\r
+------------------------------------------------------------------------------*/\r
+\r
+DefinitionBlock (\r
+ "CPUPM.aml",\r
+ "SSDT",\r
+ 0x01,\r
+ "PmRef",\r
+ "CpuPm",\r
+ 0x3000\r
+ )\r
+{\r
+ External(\_PR.CPU0, DeviceObj)\r
+ External(\_PR.CPU1, DeviceObj)\r
+ External(\_PR.CPU2, DeviceObj)\r
+ External(\_PR.CPU3, DeviceObj)\r
+ External(SMIF)\r
+\r
+ Scope(\)\r
+ {\r
+\r
+ // Package of pointers to SSDT's\r
+ //\r
+ // First column is SSDT name, used for debug only.\r
+ // (First column must be EXACTLY eight characters.)\r
+ // Second column is physical address.\r
+ // Third column is table length.\r
+ //\r
+ // IF modifying this file, see warnings listed in ppminit.asm.\r
+ //\r
+ Name(SSDT,Package()\r
+ {\r
+ "CPU0IST ", 0x80000000, 0x80000000,\r
+ "APIST ", 0x80000000, 0x80000000,\r
+ "CPU0CST ", 0x80000000, 0x80000000,\r
+ "APCST ", 0x80000000, 0x80000000\r
+ })\r
+\r
+ //\r
+ // Note: See PpmBiosInit in PPMINIT.ASM for a definition of\r
+ // the PpmFlags mirrored in CFGD.\r
+ //\r
+ Name(CFGD, 0x80000000)\r
+\r
+ Name(\PDC0,0x80000000) // CPU0 _PDC Flags.\r
+ Name(\PDC1,0x80000000) // CPU1 _PDC Flags.\r
+ Name(\PDC2,0x80000000) // CPU2 _PDC Flags.\r
+ Name(\PDC3,0x80000000) // CPU3 _PDC Flags.\r
+ Name(\SDTL,0x00) // Loaded SSDT Flags.\r
+ }\r
+\r
+ Scope(\_PR.CPU0)\r
+ {\r
+ //\r
+ // Define handles for opregions (used by load.)\r
+ //\r
+ Name(HI0,0) // Handle to CPU0IST\r
+ Name(HC0,0) // Handle to CPU0CST\r
+\r
+ Method(_PDC,1)\r
+ {\r
+ //\r
+ // Check and extract the _PDC information.\r
+ //\r
+ Store(CPDC(Arg0), Local0)\r
+ //\r
+ // Save the capability information and load tables as needed.\r
+ //\r
+ GCAP(Local0)\r
+ //\r
+ // Return status.\r
+ //\r
+ //Return (Local0)\r
+ }\r
+\r
+ Method(_OSC, 4)\r
+ {\r
+ //\r
+ // Check and extract the _OSC information.\r
+ //\r
+ Store(COSC(Arg0, Arg1, Arg2, Arg3), Local0)\r
+ //\r
+ // Save the capability information and load tables as needed.\r
+ //\r
+ GCAP(Local0)\r
+ //\r
+ // Return status.\r
+ //\r
+ Return (Local0)\r
+ }\r
+\r
+ //\r
+ // Implement a generic Method to check _PDC information which may be called\r
+ // by any of the processor scopes. (The use of _PDC is deprecated in ACPI 3.\r
+ // in favor of _OSC. However, for backwards compatibility, _PDC may be\r
+ // implemented using _OSC as follows:)\r
+ //\r
+ Method(CPDC,1)\r
+ {\r
+ CreateDwordField (Arg0, 0, REVS)\r
+ CreateDwordField (Arg0, 4, SIZE)\r
+\r
+ //\r
+ // Local0 = Number of bytes for Arg0\r
+ //\r
+ Store (SizeOf (Arg0), Local0)\r
+\r
+ //\r
+ // Local1 = Number of Capabilities bytes in Arg0\r
+ //\r
+ Store (Subtract (Local0, 8), Local1)\r
+\r
+ //\r
+ // TEMP = Temporary field holding Capability DWORDs\r
+ //\r
+ CreateField (Arg0, 64, Multiply (Local1, 8), TEMP)\r
+\r
+ //\r
+ // Create the Status (STAT) buffer with the first DWORD = 0\r
+ // This is required as per ACPI 3.0 Spec which says the\r
+ // first DWORD is used to return errors defined by _OSC.\r
+ //\r
+ Name (STS0, Buffer () {0x00, 0x00, 0x00, 0x00})\r
+\r
+ //\r
+ // Concatenate the _PDC capabilities bytes to the STS0 Buffer\r
+ // and store them in a local variable for calling OSC\r
+ //\r
+ Concatenate (STS0, TEMP, Local2)\r
+\r
+ Return(COSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE, Local2))\r
+ }\r
+\r
+ //\r
+ // Implement a generic Method to check _OSC information which may be called\r
+ // by any of the processor scopes.\r
+ //\r
+ Method(COSC, 4)\r
+ {\r
+ //\r
+ // Point to Status DWORD in the Arg3 buffer (STATUS)\r
+ //\r
+ CreateDWordField(Arg3, 0, STS0)\r
+ //\r
+ // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES)\r
+ //\r
+ CreateDwordField(Arg3, 4, CAP0)\r
+\r
+ //\r
+ // _OSC needs to validate the UUID and Revision.\r
+ //\r
+ // IF Unrecognized UUID\r
+ // Return Unrecognized UUID _OSC Failure\r
+ // IF Unsupported Revision\r
+ // Return Unsupported Revision _OSC Failure\r
+ //\r
+ // STS0[0] = Reserved\r
+ // STS0[1] = _OSC Failure\r
+ // STS0[2] = Unrecognized UUID\r
+ // STS0[3] = Unsupported Revision\r
+ // STS0[4] = Capabilities masked\r
+ //\r
+ // Note: The comparison method used is necessary due to\r
+ // limitations of certain OSes which cannot perform direct\r
+ // buffer comparisons.\r
+ //\r
+ // Create a set of "Input" UUID fields.\r
+ //\r
+ CreateDwordField(Arg0, 0x0, IID0)\r
+ CreateDwordField(Arg0, 0x4, IID1)\r
+ CreateDwordField(Arg0, 0x8, IID2)\r
+ CreateDwordField(Arg0, 0xC, IID3)\r
+ //\r
+ // Create a set of "Expected" UUID fields.\r
+ //\r
+ Name(UID0, ToUUID("4077A616-290C-47BE-9EBD-D87058713953"))\r
+ CreateDwordField(UID0, 0x0, EID0)\r
+ CreateDwordField(UID0, 0x4, EID1)\r
+ CreateDwordField(UID0, 0x8, EID2)\r
+ CreateDwordField(UID0, 0xC, EID3)\r
+ //\r
+ // Verify the input UUID matches the expected UUID.\r
+ //\r
+ If(LNot(LAnd(LAnd(LEqual(IID0, EID0),LEqual(IID1, EID1)),LAnd(LEqual(IID2, EID2),LEqual(IID3, EID3)))))\r
+ {\r
+ //\r
+ // Return Unrecognized UUID _OSC Failure\r
+ //\r
+ Store (0x6, STS0)\r
+ Return (Arg3)\r
+ }\r
+\r
+ If(LNot(LEqual(Arg1,1)))\r
+ {\r
+ //\r
+ // Return Unsupported Revision _OSC Failure\r
+ //\r
+ Store (0xA, STS0)\r
+ Return (Arg3)\r
+ }\r
+\r
+ Return (Arg3)\r
+ }\r
+\r
+ //\r
+ // Get the capability information and load appropriate tables as needed.\r
+ //\r
+ Method(GCAP, 1)\r
+ {\r
+\r
+ // Point to Status DWORD in the Arg0 buffer (STATUS)\r
+ CreateDWordField(Arg0, 0, STS0)\r
+\r
+ // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)\r
+ CreateDwordField(Arg0, 4, CAP0)\r
+\r
+ //\r
+ // If the UUID was unrecognized or the _OSC revision was unsupported,\r
+ // return without updating capabilities.\r
+ //\r
+ If(LOr(LEqual(STS0,0x6),LEqual(STS0,0xA)))\r
+ {\r
+ Return()\r
+ }\r
+\r
+ //\r
+ // Check if this is a query (BIT0 of Status = 1).\r
+ // If so, mask off the bits we support and return.\r
+ //\r
+ if (And(STS0, 1))\r
+ {\r
+ And(CAP0, 0xBFF, CAP0)\r
+ Return()\r
+ }\r
+\r
+ //\r
+ // Store result of PDC. (We clear out the MSB, which was just\r
+ // used as a placeholder for the compiler; and then "OR" the\r
+ // value in case we get multiple calls, each of which only\r
+ // reports partial support.)\r
+ //\r
+ Or(And(PDC0, 0x7FFFFFFF), CAP0, PDC0)\r
+\r
+ //\r
+ // Check IF the IST SSDTs should be loaded.\r
+ //\r
+ // CFGD[0] = GV3 Capable/Enabled\r
+ //\r
+ If(And(CFGD,0x01))\r
+ {\r
+ //\r
+ // Load the IST SSDTs if:\r
+ // (1) CMP capable and enabled.\r
+ // (2) Driver supports P-States in MP configurations\r
+ // (3) Driver supports direct HW P-State control\r
+ // (4) SSDT is not already loaded\r
+ //\r
+ // CFGD[24] = Two or more cores enabled\r
+ // PDCx[3] = OS supports C1 and P-states in MP systems\r
+ // PDCx[0] = OS supports direct access of the perf MSR\r
+ // SDTL[0] = CPU0 IST SSDT Loaded\r
+ //\r
+ If(LAnd(LAnd(And(CFGD,0x01000000),LEqual(And(PDC0, 0x0009), 0x0009)),LNot(And(SDTL,0x01))))\r
+ {\r
+ //\r
+ // Flag the IST SSDT as loaded for CPU0\r
+ //\r
+ Or(SDTL, 0x01, SDTL)\r
+\r
+ OperationRegion(IST0,SystemMemory,DeRefOf(Index(SSDT,1)),DeRefOf(Index(SSDT,2)))\r
+ Load(IST0, HI0) // Dynamically load the CPU0IST SSDT\r
+ }\r
+ }\r
+\r
+ //\r
+ // Check IF the CST SSDTs should be loaded.\r
+ //\r
+ // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled\r
+ //\r
+ If(And(CFGD,0x82))\r
+ {\r
+ //\r
+ // Load the CST SSDTs if:\r
+ // (1) CMP capable/enabled\r
+ // (2) Driver supports multi-processor configurations\r
+ // (3) CPU0 CST ISDT is not already loaded\r
+ //\r
+ // CFGD[24] = Two or more cores enabled\r
+ // PDCx[3] = OS supports C1 and P-states in MP systems\r
+ // PDCx[4] = OS supports ind. C2/C3 in MP systems\r
+ // SDTL[1] = CPU0 CST SSDT Loaded\r
+ //\r
+ If(LAnd(LAnd(And(CFGD,0x01000000),And(PDC0,0x0018)),LNot(And(SDTL,0x02))))\r
+ {\r
+ //\r
+ // Flag the CST SSDT as loaded for CPU0\r
+ //\r
+ Or(SDTL, 0x02, SDTL)\r
+\r
+ OperationRegion(CST0,SystemMemory,DeRefOf(Index(SSDT,7)),DeRefOf(Index(SSDT,8)))\r
+ Load(CST0, HC0) // Dynamically load the CPU0CST SSDT\r
+ }\r
+ }\r
+\r
+ Return ()\r
+ }\r
+ }\r
+\r
+\r
+ Scope(\_PR.CPU1)\r
+ {\r
+ //\r
+ // Define handles for opregions (used by load.)\r
+ //\r
+ Name(HI1,0) // Handle to APIST\r
+ Name(HC1,0) // Handle to APCST\r
+\r
+ Method(_PDC,1)\r
+ {\r
+ //\r
+ // Refer to \_PR.CPU0._PDC for description.\r
+ //\r
+ Store(\_PR.CPU0.CPDC(Arg0), Local0)\r
+ GCAP(Local0)\r
+ //Return (Local0)\r
+ }\r
+\r
+ Method(_OSC, 4)\r
+ {\r
+ //\r
+ // Refer to \_PR.CPU0._OSC for description.\r
+ //\r
+ Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)\r
+ GCAP(Local0)\r
+ Return (Local0)\r
+ }\r
+\r
+ //\r
+ // Get the capability information and load appropriate tables as needed.\r
+ //\r
+ Method(GCAP, 1)\r
+ {\r
+ //\r
+ // Point to Status DWORD in the Arg0 buffer (STATUS)\r
+ //\r
+ CreateDWordField(Arg0, 0, STS1)\r
+ //\r
+ // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)\r
+ //\r
+ CreateDwordField(Arg0, 4, CAP1)\r
+ //\r
+ // If the UUID was unrecognized or the _OSC revision was unsupported,\r
+ // return without updating capabilities.\r
+ //\r
+ If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))\r
+ {\r
+ Return()\r
+ }\r
+\r
+ //\r
+ // Check if this is a query (BIT0 of Status = 1).\r
+ // If so, mask off the bits we support and return.\r
+ //\r
+ if (And(STS1, 1))\r
+ {\r
+ And(CAP1, 0xBFF, CAP1)\r
+ Return()\r
+ }\r
+\r
+ //\r
+ // Store result of PDC. (We clear out the MSB, which was just\r
+ // used as a placeholder for the compiler; and then "OR" the\r
+ // value in case we get multiple calls, each of which only\r
+ // reports partial support.)\r
+ //\r
+ Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)\r
+\r
+ //\r
+ // Attempt to dynamically load the IST SSDTs if:\r
+ // (1) Driver supports P-States in MP configurations\r
+ // (2) Driver supports direct HW P-State control\r
+ //\r
+ // PDCx[3] = OS supports C1 and P-states in MP systems\r
+ // PDCx[0] = OS supports direct access of the perf MSR\r
+ //\r
+ If(LEqual(And(PDC0, 0x0009), 0x0009))\r
+ {\r
+ APPT()\r
+ }\r
+\r
+ //\r
+ // Load the CST SSDTs if:\r
+ // (1) Driver supports multi-processor configurations\r
+ //\r
+ // PDCx[3] = OS supports C1 and P-states in MP systems\r
+ // PDCx[4] = OS supports ind. C2/C3 in MP systems\r
+ //\r
+ If(And(PDC0,0x0018))\r
+ {\r
+ APCT()\r
+ }\r
+\r
+ Return()\r
+ }\r
+\r
+ //\r
+ // Dynamically load the CST SSDTs if:\r
+ // (1) C-States are enabled\r
+ // (2) SSDT is not already loaded\r
+ //\r
+ // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled\r
+ // SDTL[5] = AP CST SSDT Loaded\r
+ //\r
+ Method(APCT,0)\r
+ {\r
+ If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))\r
+ {\r
+ //\r
+ // Flag the CST SSDT as loaded for the AP's\r
+ //\r
+ Or(SDTL, 0x20, SDTL)\r
+ //\r
+ // Dynamically load the APCST SSDT\r
+ //\r
+ OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))\r
+ Load(CST1, HC1)\r
+ }\r
+ }\r
+\r
+ //\r
+ // Dynamically load the IST SSDTs if:\r
+ // (1) If GV3 capable and enabled\r
+ // (2) SSDT is not already loaded\r
+ //\r
+ // CFGD[0] = GV3 Capable/Enabled\r
+ // SDTL[4] = AP IST SSDT Loaded\r
+ //\r
+ Method(APPT,0)\r
+ {\r
+ If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))\r
+ {\r
+ //\r
+ // Flag the IST SSDT as loaded for CPU0\r
+ //\r
+ Or(SDTL, 0x10, SDTL)\r
+\r
+ OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))\r
+ Load(IST1, HI1) // Dynamically load the CPU1IST SSDT\r
+ }\r
+ }\r
+ } // End CPU1\r
+\r
+ Scope(\_PR.CPU2)\r
+ {\r
+ //\r
+ // Define handles for opregions (used by load.)\r
+ //\r
+ Name(HI1,0) // Handle to APIST\r
+ Name(HC1,0) // Handle to APCST\r
+\r
+ Method(_PDC,1)\r
+ {\r
+ //\r
+ // Refer to \_PR.CPU0._PDC for description.\r
+ //\r
+ Store(\_PR.CPU0.CPDC(Arg0), Local0)\r
+ GCAP(Local0)\r
+ //Return (Local0)\r
+ }\r
+\r
+ Method(_OSC, 4)\r
+ {\r
+ //\r
+ // Refer to \_PR.CPU0._OSC for description.\r
+ //\r
+ Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)\r
+ GCAP(Local0)\r
+ Return (Local0)\r
+ }\r
+\r
+ //\r
+ // Get the capability information and load appropriate tables as needed.\r
+ //\r
+ Method(GCAP, 1)\r
+ {\r
+ //\r
+ // Point to Status DWORD in the Arg0 buffer (STATUS)\r
+ //\r
+ CreateDWordField(Arg0, 0, STS1)\r
+ //\r
+ // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)\r
+ //\r
+ CreateDwordField(Arg0, 4, CAP1)\r
+ //\r
+ // If the UUID was unrecognized or the _OSC revision was unsupported,\r
+ // return without updating capabilities.\r
+ //\r
+ If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))\r
+ {\r
+ Return()\r
+ }\r
+\r
+ //\r
+ // Check if this is a query (BIT0 of Status = 1).\r
+ // If so, mask off the bits we support and return.\r
+ //\r
+ if (And(STS1, 1))\r
+ {\r
+ And(CAP1, 0xBFF, CAP1)\r
+ Return()\r
+ }\r
+\r
+ //\r
+ // Store result of PDC. (We clear out the MSB, which was just\r
+ // used as a placeholder for the compiler; and then "OR" the\r
+ // value in case we get multiple calls, each of which only\r
+ // reports partial support.)\r
+ //\r
+ Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)\r
+\r
+ //\r
+ // Attempt to dynamically load the IST SSDTs if:\r
+ // (1) Driver supports P-States in MP configurations\r
+ // (2) Driver supports direct HW P-State control\r
+ //\r
+ // PDCx[3] = OS supports C1 and P-states in MP systems\r
+ // PDCx[0] = OS supports direct access of the perf MSR\r
+ //\r
+ If(LEqual(And(PDC0, 0x0009), 0x0009))\r
+ {\r
+ APPT()\r
+ }\r
+\r
+ //\r
+ // Load the CST SSDTs if:\r
+ // (1) Driver supports multi-processor configurations\r
+ //\r
+ // PDCx[3] = OS supports C1 and P-states in MP systems\r
+ // PDCx[4] = OS supports ind. C2/C3 in MP systems\r
+ //\r
+ If(And(PDC0,0x0018))\r
+ {\r
+ APCT()\r
+ }\r
+\r
+ Return()\r
+ }\r
+\r
+ //\r
+ // Dynamically load the CST SSDTs if:\r
+ // (1) C-States are enabled\r
+ // (2) SSDT is not already loaded\r
+ //\r
+ // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled\r
+ // SDTL[5] = AP CST SSDT Loaded\r
+ //\r
+ Method(APCT,0)\r
+ {\r
+ If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))\r
+ {\r
+ //\r
+ // Flag the CST SSDT as loaded for the AP's\r
+ //\r
+ Or(SDTL, 0x20, SDTL)\r
+ //\r
+ // Dynamically load the APCST SSDT\r
+ //\r
+ OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))\r
+ Load(CST1, HC1)\r
+ }\r
+ }\r
+\r
+ //\r
+ // Dynamically load the IST SSDTs if:\r
+ // (1) If GV3 capable and enabled\r
+ // (2) SSDT is not already loaded\r
+ //\r
+ // CFGD[0] = GV3 Capable/Enabled\r
+ // SDTL[4] = AP IST SSDT Loaded\r
+ //\r
+ Method(APPT,0)\r
+ {\r
+ If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))\r
+ {\r
+ //\r
+ // Flag the IST SSDT as loaded for CPU0\r
+ //\r
+ Or(SDTL, 0x10, SDTL)\r
+\r
+ OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))\r
+ Load(IST1, HI1) // Dynamically load the CPU1IST SSDT\r
+ }\r
+ }\r
+ } // End CPU1\r
+\r
+ Scope(\_PR.CPU3)\r
+ {\r
+ //\r
+ // Define handles for opregions (used by load.)\r
+ //\r
+ Name(HI1,0) // Handle to APIST\r
+ Name(HC1,0) // Handle to APCST\r
+\r
+ Method(_PDC,1)\r
+ {\r
+ //\r
+ // Refer to \_PR.CPU0._PDC for description.\r
+ //\r
+ Store(\_PR.CPU0.CPDC(Arg0), Local0)\r
+ GCAP(Local0)\r
+ //Return (Local0)\r
+ }\r
+\r
+ Method(_OSC, 4)\r
+ {\r
+ //\r
+ // Refer to \_PR.CPU0._OSC for description.\r
+ //\r
+ Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)\r
+ GCAP(Local0)\r
+ Return (Local0)\r
+ }\r
+\r
+ //\r
+ // Get the capability information and load appropriate tables as needed.\r
+ //\r
+ Method(GCAP, 1)\r
+ {\r
+ //\r
+ // Point to Status DWORD in the Arg0 buffer (STATUS)\r
+ //\r
+ CreateDWordField(Arg0, 0, STS1)\r
+ //\r
+ // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)\r
+ //\r
+ CreateDwordField(Arg0, 4, CAP1)\r
+ //\r
+ // If the UUID was unrecognized or the _OSC revision was unsupported,\r
+ // return without updating capabilities.\r
+ //\r
+ If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))\r
+ {\r
+ Return()\r
+ }\r
+\r
+ //\r
+ // Check if this is a query (BIT0 of Status = 1).\r
+ // If so, mask off the bits we support and return.\r
+ //\r
+ if (And(STS1, 1))\r
+ {\r
+ And(CAP1, 0xBFF, CAP1)\r
+ Return()\r
+ }\r
+\r
+ //\r
+ // Store result of PDC. (We clear out the MSB, which was just\r
+ // used as a placeholder for the compiler; and then "OR" the\r
+ // value in case we get multiple calls, each of which only\r
+ // reports partial support.)\r
+ //\r
+ Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)\r
+\r
+ //\r
+ // Attempt to dynamically load the IST SSDTs if:\r
+ // (1) Driver supports P-States in MP configurations\r
+ // (2) Driver supports direct HW P-State control\r
+ //\r
+ // PDCx[3] = OS supports C1 and P-states in MP systems\r
+ // PDCx[0] = OS supports direct access of the perf MSR\r
+ //\r
+ If(LEqual(And(PDC0, 0x0009), 0x0009))\r
+ {\r
+ APPT()\r
+ }\r
+\r
+ //\r
+ // Load the CST SSDTs if:\r
+ // (1) Driver supports multi-processor configurations\r
+ //\r
+ // PDCx[3] = OS supports C1 and P-states in MP systems\r
+ // PDCx[4] = OS supports ind. C2/C3 in MP systems\r
+ //\r
+ If(And(PDC0,0x0018))\r
+ {\r
+ APCT()\r
+ }\r
+\r
+ Return()\r
+ }\r
+\r
+ //\r
+ // Dynamically load the CST SSDTs if:\r
+ // (1) C-States are enabled\r
+ // (2) SSDT is not already loaded\r
+ //\r
+ // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled\r
+ // SDTL[5] = AP CST SSDT Loaded\r
+ //\r
+ Method(APCT,0)\r
+ {\r
+ If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))\r
+ {\r
+ //\r
+ // Flag the CST SSDT as loaded for the AP's\r
+ //\r
+ Or(SDTL, 0x20, SDTL)\r
+ //\r
+ // Dynamically load the APCST SSDT\r
+ //\r
+ OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))\r
+ Load(CST1, HC1)\r
+ }\r
+ }\r
+\r
+ //\r
+ // Dynamically load the IST SSDTs if:\r
+ // (1) If GV3 capable and enabled\r
+ // (2) SSDT is not already loaded\r
+ //\r
+ // CFGD[0] = GV3 Capable/Enabled\r
+ // SDTL[4] = AP IST SSDT Loaded\r
+ //\r
+ Method(APPT,0)\r
+ {\r
+ If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))\r
+ {\r
+ //\r
+ // Flag the IST SSDT as loaded for CPU0\r
+ //\r
+ Or(SDTL, 0x10, SDTL)\r
+\r
+ OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))\r
+ Load(IST1, HI1) // Dynamically load the CPU1IST SSDT\r
+ }\r
+ }\r
+ } // End CPU3\r
+} // End of Definition Block\r
+\r
+\r
+\r
projects / mirror_edk2.git / blobdiff