+++ /dev/null
-/*++\r
-\r
-Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
-\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-\r
---*/\r
-\r
-\r
-/*++\r
-\r
-Module Name:\r
-\r
- MMC.h\r
-\r
-Abstract:\r
-\r
- Header file for Industry MMC 4.2 spec.\r
-\r
---*/\r
-\r
-#ifndef _MMC_H\r
-#define _MMC_H\r
-\r
-#pragma pack(1)\r
-//\r
-//Command definition\r
-//\r
-\r
-#define CMD0 0\r
-#define CMD1 1\r
-#define CMD2 2\r
-#define CMD3 3\r
-#define CMD4 4\r
-#define CMD6 6\r
-#define CMD7 7\r
-#define CMD8 8\r
-#define CMD9 9\r
-#define CMD10 10\r
-#define CMD11 11\r
-#define CMD12 12\r
-#define CMD13 13\r
-#define CMD14 14\r
-#define CMD15 15\r
-#define CMD16 16\r
-#define CMD17 17\r
-#define CMD18 18\r
-#define CMD19 19\r
-#define CMD20 20\r
-#define CMD23 23\r
-#define CMD24 24\r
-#define CMD25 25\r
-#define CMD26 26\r
-#define CMD27 27\r
-#define CMD28 28\r
-#define CMD29 29\r
-#define CMD30 30\r
-#define CMD35 35\r
-#define CMD36 36\r
-#define CMD38 38\r
-#define CMD39 39\r
-#define CMD40 40\r
-#define CMD42 42\r
-#define CMD55 55\r
-#define CMD56 56\r
-\r
-\r
-\r
-#define GO_IDLE_STATE CMD0\r
-#define SEND_OP_COND CMD1\r
-#define ALL_SEND_CID CMD2\r
-#define SET_RELATIVE_ADDR CMD3\r
-#define SET_DSR CMD4\r
-#define SWITCH CMD6\r
-#define SELECT_DESELECT_CARD CMD7\r
-#define SEND_EXT_CSD CMD8\r
-#define SEND_CSD CMD9\r
-#define SEND_CID CMD10\r
-#define READ_DAT_UNTIL_STOP CMD11\r
-#define STOP_TRANSMISSION CMD12\r
-#define SEND_STATUS CMD13\r
-#define BUSTEST_R CMD14\r
-#define GO_INACTIVE_STATE CMD15\r
-#define SET_BLOCKLEN CMD16\r
-#define READ_SINGLE_BLOCK CMD17\r
-#define READ_MULTIPLE_BLOCK CMD18\r
-#define BUSTEST_W CMD19\r
-#define WRITE_DAT_UNTIL_STOP CMD20\r
-#define SET_BLOCK_COUNT CMD23\r
-#define WRITE_BLOCK CMD24\r
-#define WRITE_MULTIPLE_BLOCK CMD25\r
-#define PROGRAM_CID CMD26\r
-#define PROGRAM_CSD CMD27\r
-#define SET_WRITE_PROT CMD28\r
-#define CLR_WRITE_PROT CMD29\r
-#define SEND_WRITE_PROT CMD30\r
-#define ERASE_GROUP_START CMD35\r
-#define ERASE_GROUP_END CMD36\r
-#define ERASE CMD38\r
-#define FAST_IO CMD39\r
-#define GO_IRQ_STATE CMD40\r
-#define LOCK_UNLOCK CMD42\r
-#define APP_CMD CMD55\r
-#define GEN_CMD CMD56\r
-\r
-#define B_PERM_WP_DIS 0x10\r
-#define B_PWR_WP_EN 0x01\r
-#define US_PERM_WP_DIS 0x10\r
-#define US_PWR_WP_EN 0x01\r
-\r
-#define FREQUENCY_OD (400 * 1000)\r
-#define FREQUENCY_MMC_PP (26 * 1000 * 1000)\r
-#define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000)\r
-\r
-#define DEFAULT_DSR_VALUE 0x404\r
-\r
-//\r
-//Registers definition\r
-//\r
-\r
-typedef struct {\r
- UINT32 Reserved0: 7; // 0\r
- UINT32 V170_V195: 1; // 1.70V - 1.95V\r
- UINT32 V200_V260: 7; // 2.00V - 2.60V\r
- UINT32 V270_V360: 9; // 2.70V - 3.60V\r
- UINT32 Reserved1: 5; // 0\r
- UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)\r
- UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine\r
-} OCR;\r
-\r
-\r
-typedef struct {\r
- UINT8 NotUsed: 1; // 1\r
- UINT8 CRC: 7; // CRC7 checksum\r
- UINT8 MDT; // Manufacturing date\r
- UINT32 PSN; // Product serial number\r
- UINT8 PRV; // Product revision\r
- UINT8 PNM[6]; // Product name\r
- UINT16 OID; // OEM/Application ID\r
- UINT8 MID; // Manufacturer ID\r
-} CID;\r
-\r
-\r
-typedef struct {\r
- UINT8 NotUsed: 1; // 1 [0:0]\r
- UINT8 CRC: 7; // CRC [7:1]\r
- UINT8 ECC: 2; // ECC code [9:8]\r
- UINT8 FILE_FORMAT: 2; // File format [11:10]\r
- UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]\r
- UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]\r
- UINT8 COPY: 1; // Copy flag (OTP) [14:14]\r
- UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]\r
- UINT16 CONTENT_PROT_APP: 1; // Content protection application [16:16]\r
- UINT16 Reserved0: 4; // 0 [20:17]\r
- UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]\r
- UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]\r
- UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]\r
- UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]\r
- UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]\r
- UINT32 WP_GRP_SIZE: 5; // Write protect group size [36:32]\r
- UINT32 ERASE_GRP_MULT: 5; // Erase group size multiplier [41:37]\r
- UINT32 ERASE_GRP_SIZE: 5; // Erase group size [46:42]\r
- UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]\r
- UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]\r
- UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]\r
- UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]\r
- UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]\r
- UINT32 C_SIZELow2: 2;// Device size [73:62]\r
- UINT32 C_SIZEHigh10: 10;// Device size [73:62]\r
- UINT32 Reserved1: 2; // 0 [75:74]\r
- UINT32 DSR_IMP: 1; // DSR implemented [76:76]\r
- UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]\r
- UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]\r
- UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]\r
- UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]\r
- UINT32 CCC: 12;// Card command classes [95:84]\r
- UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]\r
- UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r
- UINT8 TAAC ; // Data read access-time 1 [119:112]\r
- UINT8 Reserved2: 2; // 0 [121:120]\r
- UINT8 SPEC_VERS: 4; // System specification version [125:122]\r
- UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]\r
-} CSD;\r
-\r
-typedef struct {\r
- UINT8 Reserved133_0[134]; // [133:0] 0\r
- UINT8 SEC_BAD_BLOCK_MGMNT; // [134] Bad Block Management mode\r
- UINT8 Reserved135; // [135] 0\r
- UINT8 ENH_START_ADDR[4]; // [139:136] Enhanced User Data Start Address\r
- UINT8 ENH_SIZE_MULT[3]; // [142:140] Enhanced User Data Start Size\r
- UINT8 GP_SIZE_MULT_1[3]; // [145:143] GPP1 Size\r
- UINT8 GP_SIZE_MULT_2[3]; // [148:146] GPP2 Size\r
- UINT8 GP_SIZE_MULT_3[3]; // [151:149] GPP3 Size\r
- UINT8 GP_SIZE_MULT_4[3]; // [154:152] GPP4 Size\r
- UINT8 PARTITION_SETTING_COMPLETED; // [155] Partitioning Setting\r
- UINT8 PARTITIONS_ATTRIBUTES; // [156] Partitions attributes\r
- UINT8 MAX_ENH_SIZE_MULT[3]; // [159:157] GPP4 Start Size\r
- UINT8 PARTITIONING_SUPPORT; // [160] Partitioning Support\r
- UINT8 HPI_MGMT; // [161] HPI management\r
- UINT8 RST_n_FUNCTION; // [162] H/W reset function\r
- UINT8 BKOPS_EN; // [163] Enable background operations handshake\r
- UINT8 BKOPS_START; // [164] Manually start background operations\r
- UINT8 Reserved165; // [165] 0\r
- UINT8 WR_REL_PARAM; // [166] Write reliability parameter register\r
- UINT8 WR_REL_SET; // [167] Write reliability setting register\r
- UINT8 RPMB_SIZE_MULT; // [168] RPMB Size\r
- UINT8 FW_CONFIG; // [169] FW configuration\r
- UINT8 Reserved170; // [170] 0\r
- UINT8 USER_WP; // [171] User area write protection\r
- UINT8 Reserved172; // [172] 0\r
- UINT8 BOOT_WP; // [173] Boot area write protection\r
- UINT8 Reserved174; // [174] 0\r
- UINT8 ERASE_GROUP_DEF; // [175] High density erase group definition\r
- UINT8 Reserved176; // [176] 0\r
- UINT8 BOOT_BUS_WIDTH; // [177] Boot bus width\r
- UINT8 BOOT_CONFIG_PROT; // [178] Boot config protection\r
- UINT8 PARTITION_CONFIG; // [179] Partition config\r
- UINT8 Reserved180; // [180] 0\r
- UINT8 ERASED_MEM_CONT; // [181] Erased Memory Content\r
- UINT8 Reserved182; // [182] 0\r
- UINT8 BUS_WIDTH; // [183] Bus Width Mode\r
- UINT8 Reserved184; // [184] 0\r
- UINT8 HS_TIMING; // [185] High Speed Interface Timing\r
- UINT8 Reserved186; // [186] 0\r
- UINT8 POWER_CLASS; // [187] Power Class\r
- UINT8 Reserved188; // [188] 0\r
- UINT8 CMD_SET_REV; // [189] Command Set Revision\r
- UINT8 Reserved190; // [190] 0\r
- UINT8 CMD_SET; // [191] Command Set\r
- UINT8 EXT_CSD_REV; // [192] Extended CSD Revision\r
- UINT8 Reserved193; // [193] 0\r
- UINT8 CSD_STRUCTURE; // [194] CSD Structure Version\r
- UINT8 Reserved195; // [195] 0\r
- UINT8 CARD_TYPE; // [196] Card Type\r
- UINT8 Reserved197; // [197] 0\r
- UINT8 OUT_OF_INTERRUPT_TIME; // [198] Out-of-interrupt busy timing\r
- UINT8 PARTITION_SWITCH_TIME; // [199] Partition switching timing\r
- UINT8 PWR_CL_52_195; // [200] Power Class for 52MHz @ 1.95V\r
- UINT8 PWR_CL_26_195; // [201] Power Class for 26MHz @ 1.95V\r
- UINT8 PWR_CL_52_360; // [202] Power Class for 52MHz @ 3.6V\r
- UINT8 PWR_CL_26_360; // [203] Power Class for 26MHz @ 3.6V\r
- UINT8 Reserved204; // [204] 0\r
- UINT8 MIN_PERF_R_4_26; // [205] Minimum Read Performance for 4bit @26MHz\r
- UINT8 MIN_PERF_W_4_26; // [206] Minimum Write Performance for 4bit @26MHz\r
- UINT8 MIN_PERF_R_8_26_4_52; // [207] Minimum Read Performance for 8bit @26MHz/4bit @52MHz\r
- UINT8 MIN_PERF_W_8_26_4_52; // [208] Minimum Write Performance for 8bit @26MHz/4bit @52MHz\r
- UINT8 MIN_PERF_R_8_52; // [209] Minimum Read Performance for 8bit @52MHz\r
- UINT8 MIN_PERF_W_8_52; // [210] Minimum Write Performance for 8bit @52MHz\r
- UINT8 Reserved211; // [211] 0\r
- UINT8 SEC_COUNT[4]; // [215:212] Sector Count\r
- UINT8 Reserved216; // [216] 0\r
- UINT8 S_A_TIMEOUT; // [217] Sleep/awake timeout\r
- UINT8 Reserved218; // [218] 0\r
- UINT8 S_C_VCCQ; // [219] Sleep current (VCCQ)\r
- UINT8 S_C_VCC; // [220] Sleep current (VCC)\r
- UINT8 HC_WP_GRP_SIZE; // [221] High-capacity write protect group size\r
- UINT8 REL_WR_SEC_C; // [222] Reliable write sector count\r
- UINT8 ERASE_TIMEOUT_MULT; // [223] High-capacity erase timeout\r
- UINT8 HC_ERASE_GRP_SIZE; // [224] High-capacity erase unit size\r
- UINT8 ACC_SIZE; // [225] Access size\r
- UINT8 BOOT_SIZE_MULTI; // [226] Boot partition size\r
- UINT8 Reserved227; // [227] 0\r
- UINT8 BOOT_INFO; // [228] Boot information\r
- UINT8 SEC_TRIM_MULT; // [229] Secure TRIM Multiplier\r
- UINT8 SEC_ERASE_MULT; // [230] Secure Erase Multiplier\r
- UINT8 SEC_FEATURE_SUPPORT; // [231] Secure Feature support\r
- UINT8 TRIM_MULT; // [232] TRIM Multiplier\r
- UINT8 Reserved233; // [233] 0\r
- UINT8 MIN_PERF_DDR_R_8_52; // [234] Min Read Performance for 8-bit @ 52MHz\r
- UINT8 MIN_PERF_DDR_W_8_52; // [235] Min Write Performance for 8-bit @ 52MHz\r
- UINT8 Reserved237_236[2]; // [237:236] 0\r
- UINT8 PWR_CL_DDR_52_195; // [238] Power class for 52MHz, DDR at 1.95V\r
- UINT8 PWR_CL_DDR_52_360; // [239] Power class for 52MHz, DDR at 3.6V\r
- UINT8 Reserved240; // [240] 0\r
- UINT8 INI_TIMEOUT_AP; // [241] 1st initialization time after partitioning\r
- UINT8 CORRECTLY_PRG_SECTORS_NUM[4]; // [245:242] Number of correctly programmed sectors\r
- UINT8 BKOPS_STATUS; // [246] Background operations status\r
- UINT8 Reserved501_247[255]; // [501:247] 0\r
- UINT8 BKOPS_SUPPORT; // [502] Background operations support\r
- UINT8 HPI_FEATURES; // [503] HPI features\r
- UINT8 S_CMD_SET; // [504] Sector Count\r
- UINT8 Reserved511_505[7]; // [511:505] Sector Count\r
-} EXT_CSD;\r
-\r
-\r
-//\r
-//Card Status definition\r
-//\r
-typedef struct {\r
- UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode\r
- UINT32 Reserved1: 2; //Reserved for Application Specific commands\r
- UINT32 Reserved2: 1; //\r
- UINT32 SAPP_CMD: 1; //\r
- UINT32 Reserved3: 1; //Reserved\r
- UINT32 SWITCH_ERROR: 1; //\r
- UINT32 READY_FOR_DATA: 1; //\r
- UINT32 CURRENT_STATE: 4; //\r
- UINT32 ERASE_RESET: 1; //\r
- UINT32 Reserved4: 1; //Reserved\r
- UINT32 WP_ERASE_SKIP: 1; //\r
- UINT32 CID_CSD_OVERWRITE: 1; //\r
- UINT32 OVERRUN: 1; //\r
- UINT32 UNDERRUN: 1; //\r
- UINT32 ERROR: 1; //\r
- UINT32 CC_ERROR: 1; //\r
- UINT32 CARD_ECC_FAILED: 1; //\r
- UINT32 ILLEGAL_COMMAND: 1; //\r
- UINT32 COM_CRC_ERROR: 1; //\r
- UINT32 LOCK_UNLOCK_FAILED: 1; //\r
- UINT32 CARD_IS_LOCKED: 1; //\r
- UINT32 WP_VIOLATION: 1; //\r
- UINT32 ERASE_PARAM: 1; //\r
- UINT32 ERASE_SEQ_ERROR: 1; //\r
- UINT32 BLOCK_LEN_ERROR: 1; //\r
- UINT32 ADDRESS_MISALIGN: 1; //\r
- UINT32 ADDRESS_OUT_OF_RANGE:1; //\r
-} CARD_STATUS;\r
-\r
-typedef struct {\r
- UINT32 CmdSet: 3;\r
- UINT32 Reserved0: 5;\r
- UINT32 Value: 8;\r
- UINT32 Index: 8;\r
- UINT32 Access: 2;\r
- UINT32 Reserved1: 6;\r
-} SWITCH_ARGUMENT;\r
-\r
-#define CommandSet_Mode 0\r
-#define SetBits_Mode 1\r
-#define ClearBits_Mode 2\r
-#define WriteByte_Mode 3\r
-\r
-\r
-#define Idle_STATE 0\r
-#define Ready_STATE 1\r
-#define Ident_STATE 2\r
-#define Stby_STATE 3\r
-#define Tran_STATE 4\r
-#define Data_STATE 5\r
-#define Rcv_STATE 6\r
-#define Prg_STATE 7\r
-#define Dis_STATE 8\r
-#define Btst_STATE 9\r
-\r
-\r
-\r
-#pragma pack()\r
-#endif\r
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