Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to

[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / PchRegs / PchRegsRcrb.h

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsRcrb.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsRcrb.h
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+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchRegsRcrb.h\r
+\r
+  @brief\r
+  Register names for VLV Chipset Configuration Registers\r
+\r
+  Conventions:\r
+\r
+  - Prefixes:\r
+    Definitions beginning with "R_" are registers\r
+    Definitions beginning with "B_" are bits within registers\r
+    Definitions beginning with "V_" are meaningful values of bits within the registers\r
+    Definitions beginning with "S_" are register sizes\r
+    Definitions beginning with "N_" are the bit position\r
+  - In general, PCH registers are denoted by "_PCH_" in register names\r
+  - Registers / bits that are different between PCH generations are denoted by\r
+    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
+    at the end of the register/bit names\r
+  - Registers / bits of new devices introduced in a PCH generation will be just named\r
+    as "_PCH_" without <generation_name> inserted.\r
+\r
+**/\r
+#ifndef _PCH_REGS_RCRB_H_\r
+#define _PCH_REGS_RCRB_H_\r
+\r
+///\r
+/// Chipset Configuration Registers (Memory space)\r
+/// RCBA\r
+///\r
+#define R_PCH_RCRB_GCS                    0x00  // General Control and Status\r
+#define B_PCH_RCRB_GCS_BBSIZE             (BIT30 | BIT29) // Boot Block Size\r
+#define B_PCH_RCRB_GCS_BBS                (BIT11 | BIT10) // Boot BIOS Straps\r
+#define V_PCH_RCRB_GCS_BBS_SPI            (3 << 10) // Boot BIOS strapped to SPI\r
+#define V_PCH_RCRB_GCS_BBS_LPC            (0 << 10) // Boot BIOS strapped to LPC\r
+#define B_PCH_RCRB_GCS_TS                 BIT1 // Top Swap\r
+#define B_PCH_RCRB_GCS_BILD               BIT0 // BIOS Interface Lock-Down\r
+\r
+\r
+#endif\r