]> git.proxmox.com Git - mirror_edk2.git/blobdiff - Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPlatformPolicy.h
edk2: Remove packages moved to edk2-platforms
[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / Ppi / PchPlatformPolicy.h
diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPlatformPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPlatformPolicy.h
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-/**\r
-**/\r
-/**\r
-\r
-Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
-\r
-  SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-\r
-\r
-  @file\r
-  PchPlatformPolicy.h\r
-\r
-  @brief\r
-  PCH policy PPI produced by a platform driver specifying various\r
-  expected PCH settings. This PPI is consumed by the PCH PEI modules.\r
-\r
-**/\r
-#ifndef PCH_PLATFORM_POLICY_H_\r
-#define PCH_PLATFORM_POLICY_H_\r
-//\r
-// External include files do NOT need to be explicitly specified in real EDKII\r
-// environment\r
-//\r
-\r
-\r
-#include "PchRegs.h"\r
-\r
-//\r
-#define PCH_PLATFORM_POLICY_PPI_GUID \\r
-  { \\r
-    0x15344673, 0xd365, 0x4be2, 0x85, 0x13, 0x14, 0x97, 0xcc, 0x7, 0x61, 0x1d \\r
-  }\r
-\r
-extern EFI_GUID                         gPchPlatformPolicyPpiGuid;\r
-\r
-///\r
-/// Forward reference for ANSI C compatibility\r
-///\r
-typedef struct _PCH_PLATFORM_POLICY_PPI PCH_PLATFORM_POLICY_PPI;\r
-\r
-///\r
-/// PPI revision number\r
-/// Any backwards compatible changes to this PPI will result in an update in the revision number\r
-/// Major changes will require publication of a new PPI\r
-///\r
-/// Revision 1:    Original version\r
-///\r
-#define PCH_PLATFORM_POLICY_PPI_REVISION_1  1\r
-#define PCH_PLATFORM_POLICY_PPI_REVISION_2  2\r
-#define PCH_PLATFORM_POLICY_PPI_REVISION_3  3\r
-#define PCH_PLATFORM_POLICY_PPI_REVISION_4  4\r
-#define PCH_PLATFORM_POLICY_PPI_REVISION_5  5\r
-//\r
-// Generic definitions for device enabling/disabling used by PCH code.\r
-//\r
-#define PCH_DEVICE_ENABLE   1\r
-#define PCH_DEVICE_DISABLE  0\r
-\r
-typedef struct {\r
-  UINT8  ThermalDataReportEnable  : 1;   // OBSOLETE from Revision 5 !!! DO NOT USE !!!\r
-  UINT8  MchTempReadEnable        : 1;\r
-  UINT8  PchTempReadEnable        : 1;\r
-  UINT8  CpuEnergyReadEnable      : 1;\r
-  UINT8  CpuTempReadEnable        : 1;\r
-  UINT8  Cpu2TempReadEnable       : 1;\r
-  UINT8  TsOnDimmEnable           : 1;\r
-  UINT8  Dimm1TempReadEnable      : 1;\r
-\r
-  UINT8  Dimm2TempReadEnable      : 1;\r
-  UINT8  Dimm3TempReadEnable      : 1;\r
-  UINT8  Dimm4TempReadEnable      : 1;\r
-  UINT8  Rsvdbits                 : 5;\r
-} PCH_THERMAL_REPORT_CONTROL;\r
-//\r
-// ---------------------------- HPET Config -----------------------------\r
-//\r
-typedef struct {\r
-  BOOLEAN Enable; /// Determines if enable HPET function\r
-  UINT32  Base;   /// The HPET base address\r
-} PCH_HPET_CONFIG;\r
-\r
-\r
-///\r
-/// ---------------------------- SATA Config -----------------------------\r
-///\r
-typedef enum {\r
-  PchSataModeIde,\r
-  PchSataModeAhci,\r
-  PchSataModeRaid,\r
-  PchSataModeMax\r
-} PCH_SATA_MODE;\r
-\r
-///\r
-/// ---------------------------- PCI Express Config -----------------------------\r
-///\r
-typedef enum {\r
-  PchPcieAuto,\r
-  PchPcieGen1,\r
-  PchPcieGen2\r
-} PCH_PCIE_SPEED;\r
-\r
-typedef struct {\r
-  PCH_PCIE_SPEED  PcieSpeed[PCH_PCIE_MAX_ROOT_PORTS];\r
-} PCH_PCIE_CONFIG;\r
-\r
-///\r
-/// ---------------------------- IO APIC Config -----------------------------\r
-///\r
-typedef struct {\r
-  UINT8 IoApicId;\r
-} PCH_IOAPIC_CONFIG;\r
-\r
-///\r
-/// --------------------- Low Power Input Output Config ------------------------\r
-///\r
-typedef struct {\r
-  UINT8                   LpssPciModeEnabled    : 1;    /// Determines if LPSS PCI Mode enabled\r
-  UINT8                   Dma0Enabled           : 1;     /// Determines if LPSS DMA1 enabled\r
-  UINT8                   Dma1Enabled           : 1;     /// Determines if LPSS DMA2 enabled\r
-  UINT8                   I2C0Enabled           : 1;     /// Determines if LPSS I2C #1 enabled\r
-  UINT8                   I2C1Enabled           : 1;     /// Determines if LPSS I2C #2 enabled\r
-  UINT8                   I2C2Enabled           : 1;     /// Determines if LPSS I2C #3 enabled\r
-  UINT8                   I2C3Enabled           : 1;     /// Determines if LPSS I2C #4 enabled\r
-  UINT8                   I2C4Enabled           : 1;     /// Determines if LPSS I2C #5 enabled\r
-  UINT8                   I2C5Enabled           : 1;     /// Determines if LPSS I2C #6 enabled\r
-  UINT8                   I2C6Enabled           : 1;     /// Determines if LPSS I2C #7 enabled\r
-  UINT8                   Pwm0Enabled           : 1;     /// Determines if LPSS PWM #1 enabled\r
-  UINT8                   Pwm1Enabled           : 1;     /// Determines if LPSS PWM #2 enabled\r
-  UINT8                   Hsuart0Enabled        : 1;     /// Determines if LPSS HSUART #1 enabled\r
-  UINT8                   Hsuart1Enabled        : 1;     /// Determines if LPSS HSUART #2 enabled\r
-  UINT8                   SpiEnabled            : 1;     /// Determines if LPSS SPI enabled\r
-  UINT8                   Rsvdbits              : 2;\r
-} PEI_PCH_LPSS_CONFIG;\r
-\r
-///\r
-/// ------------ General PCH Platform Policy PPI definition ------------\r
-///\r
-struct _PCH_PLATFORM_POLICY_PPI {\r
-  UINT8                         Revision;\r
-  UINT8                         BusNumber;  // Bus Number of the PCH device\r
-  UINT32                        SpiBase;    // SPI Base Address.\r
-  UINT32                        PmcBase;    // PMC Base Address.\r
-  UINT32                        SmbmBase;   // SMB Memory Base Address.\r
-  UINT32                        IoBase;     // IO Base Address.\r
-  UINT32                        IlbBase;    // Intel Legacy Block Base Address.\r
-  UINT32                        PUnitBase;  // PUnit Base Address.\r
-  UINT32                        Rcba;       // Root Complex Base Address.\r
-  UINT32                        MphyBase;   // MPHY Base Address.\r
-  UINT16                        AcpiBase;   // ACPI I/O Base address.\r
-  UINT16                        GpioBase;   // GPIO Base address\r
-  PCH_HPET_CONFIG               *HpetConfig;\r
-  PCH_SATA_MODE                 SataMode;\r
-  PCH_PCIE_CONFIG               *PcieConfig;\r
-  PCH_IOAPIC_CONFIG             *IoApicConfig;\r
-  PEI_PCH_LPSS_CONFIG           *LpssConfig;\r
-  BOOLEAN                       EnableRmh;      // Determines if enable USB RMH function\r
-  BOOLEAN                       EhciPllCfgEnable;\r
-};\r
-\r
-#endif\r