+++ /dev/null
-/** @file\r
- This PEIM will parse the hoblist from fsp and report them into pei core.\r
- This file contains the main entrypoint of the PEIM.\r
-\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-\r
-\r
-#include <PiPei.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/SerialPortLib.h>\r
-\r
-#define PCI_IDX 0xCF8\r
-#define PCI_DAT 0xCFC\r
-\r
-#define PCI_LPC_BASE (0x8000F800)\r
-#define PCI_LPC_REG(x) (PCI_LPC_BASE + (x))\r
-\r
-#define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base Address\r
-#define R_PCH_LPC_PMC_BASE 0x44 // PBASE, 32bit, 512 Bytes\r
-#define B_PCH_LPC_PMC_BASE_EN BIT1 // Enable Bit\r
-#define R_PCH_PMC_GEN_PMCON_1 0x20 // General PM Configuration 1\r
-#define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR BIT14 // SUS Well Power Failure\r
-#define B_PCH_PMC_GEN_PMCON_PWROK_FLR BIT16 // PWROK Failure\r
-\r
-#define R_PCH_LPC_UART_CTRL 0x80 // UART Control\r
-#define B_PCH_LPC_UART_CTRL_COM1_EN BIT0 // COM1 Enable\r
-\r
-#define ILB_BASE_ADDRESS 0xFED08000 // ILB Memory Base Address\r
-#define R_PCH_ILB_IRQE 0x88 // IRQ Enable Control\r
-\r
-#define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address\r
-\r
-#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable\r
-#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ4 BIT4 // UART IRQ4 Enable\r
-#define PCIEX_BASE_ADDRESS 0xE0000000\r
-#define PCI_EXPRESS_BASE_ADDRESS PCIEX_BASE_ADDRESS\r
-#define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)\r
-#define SB_RCBA 0xfed1c000\r
-\r
-typedef enum {\r
- PchA0 = 0,\r
- PchA1 = 1,\r
- PchB0 = 2,\r
- PchB1 = 3,\r
- PchB2 = 4,\r
- PchB3 = 5,\r
- PchC0 = 6,\r
- PchSteppingMax\r
-} PCH_STEPPING;\r
-\r
-#define MmPciAddress( Segment, Bus, Device, Function, Register ) \\r
- ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \\r
- (UINTN)(Bus << 20) + \\r
- (UINTN)(Device << 15) + \\r
- (UINTN)(Function << 12) + \\r
- (UINTN)(Register) \\r
- )\r
-\r
-#define DEFAULT_PCI_BUS_NUMBER_PCH 0\r
-#define PCI_DEVICE_NUMBER_PCH_LPC 31\r
-#define PCI_FUNCTION_NUMBER_PCH_LPC 0\r
-\r
-#define R_PCH_LPC_RID_CC 0x08 // Revision ID & Class Code\r
-\r
-#define V_PCH_LPC_RID_0 0x01 // A0 Stepping (17 x 17)\r
-#define V_PCH_LPC_RID_1 0x02 // A0 Stepping (25 x 27)\r
-#define V_PCH_LPC_RID_2 0x03 // A1 Stepping (17 x 17)\r
-#define V_PCH_LPC_RID_3 0x04 // A1 Stepping (25 x 27)\r
-#define V_PCH_LPC_RID_4 0x05 // B0 Stepping (17 x 17)\r
-#define V_PCH_LPC_RID_5 0x06 // B0 Stepping (25 x 27)\r
-#define V_PCH_LPC_RID_6 0x07 // B1 Stepping (17 x 17)\r
-#define V_PCH_LPC_RID_7 0x08 // B1 Stepping (25 x 27)\r
-#define V_PCH_LPC_RID_8 0x09 // B2 Stepping (17 x 17)\r
-#define V_PCH_LPC_RID_9 0x0A // B2 Stepping (25 x 27)\r
-#define V_PCH_LPC_RID_A 0x0B // B3 Stepping (17 x 17)\r
-#define V_PCH_LPC_RID_B 0x0C // B3 Stepping (25 x 27)\r
-#define V_PCH_LPC_RID_C 0x0D // C0 Stepping (17 x 17)\r
-#define V_PCH_LPC_RID_D 0x0E // C0 Stepping (25 x 27)\r
-\r
-/**\r
- Return Pch stepping type\r
-\r
- @param[in] None\r
-\r
- @retval PCH_STEPPING Pch stepping type\r
-\r
-**/\r
-PCH_STEPPING\r
-EFIAPI\r
-PchStepping (\r
- VOID\r
- )\r
-{\r
- UINT8 RevId;\r
-\r
- RevId = MmioRead8 (\r
- MmPciAddress (0,\r
- DEFAULT_PCI_BUS_NUMBER_PCH,\r
- PCI_DEVICE_NUMBER_PCH_LPC,\r
- PCI_FUNCTION_NUMBER_PCH_LPC,\r
- R_PCH_LPC_RID_CC)\r
- );\r
-\r
- switch (RevId) {\r
- case V_PCH_LPC_RID_0:\r
- case V_PCH_LPC_RID_1:\r
- return PchA0;\r
- break;\r
-\r
- case V_PCH_LPC_RID_2:\r
- case V_PCH_LPC_RID_3:\r
- return PchA1;\r
- break;\r
-\r
- case V_PCH_LPC_RID_4:\r
- case V_PCH_LPC_RID_5:\r
- return PchB0;\r
- break;\r
-\r
- case V_PCH_LPC_RID_6:\r
- case V_PCH_LPC_RID_7:\r
- return PchB1;\r
- break;\r
-\r
- case V_PCH_LPC_RID_8:\r
- case V_PCH_LPC_RID_9:\r
- return PchB2;\r
- break;\r
-\r
- case V_PCH_LPC_RID_A:\r
- case V_PCH_LPC_RID_B:\r
- return PchB3;\r
- break;\r
-\r
- case V_PCH_LPC_RID_C:\r
- case V_PCH_LPC_RID_D:\r
- return PchC0;\r
- break;\r
-\r
- default:\r
- return PchSteppingMax;\r
- break;\r
-\r
- }\r
-}\r
-\r
-/**\r
- Enable legacy decoding on ICH6\r
-\r
- @param[in] none\r
-\r
- @retval EFI_SUCCESS Always returns success.\r
-\r
-**/\r
-VOID\r
-EnableInternalUart(\r
- VOID\r
- )\r
-{\r
-\r
- //\r
- // Program and enable PMC Base.\r
- //\r
- IoWrite32 (PCI_IDX, PCI_LPC_REG(R_PCH_LPC_PMC_BASE));\r
- IoWrite32 (PCI_DAT, (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));\r
-\r
- //\r
- // Enable COM1 for debug message output.\r
- //\r
- MmioAndThenOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, (UINT32) (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR + B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);\r
-\r
- //\r
- // Silicon Steppings\r
- //\r
- if (PchStepping()>= PchB0)\r
- MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ4);\r
- else\r
- MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);\r
- MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));\r
- MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L\r
- MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));\r
- MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L\r
- MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) B_PCH_LPC_UART_CTRL_COM1_EN);\r
-\r
- SerialPortInitialize ();\r
- SerialPortWrite ((UINT8 *)"EnableInternalUart!\r\n", sizeof("EnableInternalUart!\r\n") - 1);\r
-\r
- return ;\r
-}\r
projects / mirror_edk2.git / blobdiff