+++ /dev/null
-/*++\r
-\r
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
- \r\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- \r\r
-\r
-\r
-\r
-Module Name:\r
-\r
- PlatformInfo.h\r
-\r
-Abstract:\r
-\r
- GUID used for Platform Info Data entries in the HOB list.\r
-\r
---*/\r
-\r
-#ifndef _PLATFORM_INFO_GUID_H_\r
-#define _PLATFORM_INFO_GUID_H_\r
-\r
-#ifndef ECP_FLAG\r
-#include <PiPei.h>\r
-\r
-#include <Library/HobLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/SmbusLib.h>\r
-#include <IndustryStandard/SmBus.h>\r
-#endif\r
-\r
-#define PLATFORM_INFO_REVISION = 1 // Revision id for current platform information struct.\r
-\r
-//\r
-// Start::BayLake Board Defines\r
-//\r
-#define BOARD_REVISION_DEFAULT = 0xff\r
-#define UNKNOWN_FABID 0x0F\r
-#define FAB_ID_MASK 0x0F\r
-#define BOARD_ID_2 0x01\r
-#define BOARD_ID_1 0x40\r
-#define BOARD_ID_0 0x04\r
-\r
-#define BOARD_ID_DT_CRB 0x0\r
-#define BOARD_ID_DT_VLVR 0x1\r
-#define BOARD_ID_SVP_VLV 0xC\r
-#define BOARD_ID_SVP_EV_VLV 0xD\r
-//\r
-// End::BayLake Board Defines\r
-//\r
-\r
-//\r
-// Start::Alpine Valley Board Defines\r
-//\r
-#define DC_ID_DDR3L 0x00\r
-#define DC_ID_DDR3 0x04\r
-#define DC_ID_LPDDR3 0x02\r
-#define DC_ID_LPDDR2 0x06\r
-#define DC_ID_DDR4 0x01\r
-#define DC_ID_DDR3L_ECC 0x05\r
-#define DC_ID_NO_MEM 0x07\r
-//\r
-// End::Alpine Valley Board Defines\r
-//\r
-\r
-#define MAX_FAB_ID_RETRY_COUNT 100\r
-#define MAX_FAB_ID_CHECK_COUNT 3\r
-\r
-#define PLATFORM_INFO_HOB_REVISION 0x1\r
-\r
-#define EFI_PLATFORM_INFO_GUID \\r
- { \\r
- 0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \\r
- }\r
-\r
-extern EFI_GUID gEfiPlatformInfoGuid;\r
-\r
-typedef enum {\r
- FlavorUnknown = 0,\r
-\r
- //\r
- // Mobile\r
- //\r
- FlavorMobile = 1,\r
-\r
- //\r
- // Desktop\r
- //\r
- FlavorDesktop = 2,\r
-\r
- //\r
- // Tablet\r
- //\r
- FlavorTablet = 3\r
-} PLATFORM_FLAVOR;\r
-\r
-#pragma pack(1)\r
-\r
-typedef struct {\r
- UINT16 PciResourceIoBase;\r
- UINT16 PciResourceIoLimit;\r
- UINT32 PciResourceMem32Base;\r
- UINT32 PciResourceMem32Limit;\r
- UINT64 PciResourceMem64Base;\r
- UINT64 PciResourceMem64Limit;\r
- UINT64 PciExpressBase;\r
- UINT32 PciExpressSize;\r
- UINT8 PciHostAddressWidth;\r
- UINT8 PciResourceMinSecBus;\r
-} EFI_PLATFORM_PCI_DATA;\r
-\r
-typedef struct {\r
- UINT8 CpuAddressWidth;\r
- UINT32 CpuFamilyStepping;\r
-} EFI_PLATFORM_CPU_DATA;\r
-\r
-typedef struct {\r
- UINT8 SysIoApicEnable;\r
- UINT8 SysSioExist;\r
-} EFI_PLATFORM_SYS_DATA;\r
-\r
-typedef struct {\r
- UINT32 MemTolm;\r
- UINT32 MemMaxTolm;\r
- UINT32 MemTsegSize;\r
- UINT32 MemTsegBase;\r
- UINT32 MemIedSize;\r
- UINT32 MemIgdSize;\r
- UINT32 MemIgdBase;\r
- UINT32 MemIgdGttSize;\r
- UINT32 MemIgdGttBase;\r
- UINT64 MemMir0;\r
- UINT64 MemMir1;\r
- UINT32 MemConfigSize;\r
- UINT16 MmioSize;\r
- UINT8 DdrFreq;\r
- UINT8 DdrType; \r
- UINT32 MemSize;\r
- BOOLEAN EccSupport;\r
- UINT8 Reserved[3];\r
- UINT16 DimmSize[2];\r
-} EFI_PLATFORM_MEM_DATA;\r
-\r
-\r
-typedef struct {\r
- UINT32 IgdOpRegionAddress; // IGD OpRegion Starting Address\r
- UINT8 IgdBootType; // IGD Boot Display Device\r
- UINT8 IgdPanelType; // IGD Panel Type CMOs option\r
- UINT8 IgdTvFormat; // IGD TV Format CMOS option\r
- UINT8 IgdTvMinor; // IGD TV Minor Format CMOS option\r
- UINT8 IgdPanelScaling; // IGD Panel Scaling\r
- UINT8 IgdBlcConfig; // IGD BLC Configuration\r
- UINT8 IgdBiaConfig; // IGD BIA Configuration\r
- UINT8 IgdSscConfig; // IGD SSC Configuration\r
- UINT8 IgdDvmtMemSize; // IGD DVMT Memory Size\r
- UINT8 IgdFunc1Enable; // IGD Function 1 Enable\r
- UINT8 IgdHpllVco; // HPLL VCO\r
- UINT8 IgdSciSmiMode; // GMCH SMI/SCI mode (0=SCI)\r
- UINT8 IgdPAVP; // IGD PAVP data\r
-} EFI_PLATFORM_IGD_DATA;\r
-\r
-typedef enum {\r
- BOARD_ID_AV_SVP = 0x0, // Alpine Valley Board\r
- BOARD_ID_BL_RVP = 0x2, // BayLake Board (RVP)\r
- BOARD_ID_BL_FFRD8 = 0x3, // FFRD8 b'0011\r
- BOARD_ID_BL_FFRD = 0x4, // BayLake Board (FFRD)\r
- BOARD_ID_BL_RVP_DDR3L = 0x5, // BayLake Board (RVP DDR3L)\r
- BOARD_ID_BL_STHI = 0x7, // PPV- STHI Board\r
- BOARD_ID_BB_RVP = 0x20, // Bayley Bay Board\r
- BOARD_ID_BS_RVP = 0x30, // Bakersport Board\r
- BOARD_ID_CVH = 0x90, // Crestview Hills\r
- BOARD_ID_MINNOW2 = 0xA0, // MinnowBorad Max\r
- BOARD_ID_MINNOW2_TURBOT = 0xB0 // MinnowBoard Turbot\r
-\r
-} BOARD_ID_LIST;\r
-\r
-typedef enum {\r
- FAB1 = 0,\r
- FAB2 = 1,\r
- FAB3 = 2\r
-} FAB_ID_LIST;\r
-\r
-typedef enum {\r
- PR0 = 0, // FFRD PR0\r
- PR05 = 1, // FFRD PR0.3 and PR 0.5\r
- PR1 = 2, // FFRD PR1\r
- PR11 = 3 // FFRD PR1.1\r
-} FFRD_ID_LIST;\r
-\r
-\r
-//\r
-// VLV2 GPIO GROUP OFFSET\r
-//\r
-#define GPIO_SCORE_OFFSET 0x0000\r
-#define GPIO_NCORE_OFFSET 0x1000\r
-#define GPIO_SSUS_OFFSET 0x2000\r
-\r
-//\r
-// GPIO Initialization Data Structure for BayLake.\r
-// SC = SCORE, SS= SSUS\r
-// Note: NC doesn't support GPIO functionality in IO access mode, only support in MMIO access mode.\r
-//\r
-\r
-//\r
-// IO space\r
-//\r
-typedef struct{\r
- UINT32 Use_Sel_SC0;\r
- UINT32 Use_Sel_SC1;\r
- UINT32 Use_Sel_SC2;\r
- UINT32 Use_Sel_SS;\r
-\r
- UINT32 Io_Sel_SC0;\r
- UINT32 Io_Sel_SC1;\r
- UINT32 Io_Sel_SC2;\r
- UINT32 Io_Sel_SS;\r
-\r
- UINT32 GP_Lvl_SC0;\r
- UINT32 GP_Lvl_SC1;\r
- UINT32 GP_Lvl_SC2;\r
- UINT32 GP_Lvl_SS;\r
-\r
- UINT32 TPE_SC0;\r
- UINT32 TPE_SS;\r
-\r
- UINT32 TNE_SC0;\r
- UINT32 TNE_SS;\r
-\r
- UINT32 TS_SC0;\r
- UINT32 TS_SS;\r
-\r
- UINT32 WE_SS;\r
-} CFIO_INIT_STRUCT;\r
-\r
-\r
-\r
-//\r
-// CFIO PAD configuration Registers\r
-//\r
-//\r
-// Memory space\r
-//\r
-typedef union {\r
- UINT32 dw;\r
- struct {\r
- UINT32 Func_Pin_Mux:3; // 0:2 Function of CFIO selection\r
- UINT32 ipslew:2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width\r
- UINT32 inslew:2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate\r
- UINT32 Pull_assign:2; // 7:8 Pull assignment\r
- UINT32 Pull_strength:2; // 9:10 Pull strength\r
- UINT32 Bypass_flop:1; // 11 Bypass flop\r
- UINT32 Filter_en:1; // 12 Filter Enable\r
- UINT32 Hist_ctrl:2; // 13:14 hysteresis control\r
- UINT32 Hist_enb:1; // 15 Hysteresis enable, active low\r
- UINT32 Delay_line:6; // 16:21 Delay line values - Delay values for input or output\r
- UINT32 Reserved:3; // 22:24 Reserved\r
- UINT32 TPE:1; // 25 Trigger Positive Edge Enable\r
- UINT32 TNE:1; // 26 Trigger Negative Edge Enable\r
- UINT32 Reserved2:3; // 27:29 Reserved\r
- UINT32 i1p5sel:1; // 30\r
- UINT32 IODEN:1; // 31 : Open Drain enable. Active high\r
- } r;\r
-} PAD_CONF0;\r
-\r
-typedef union{\r
- UINT32 dw;\r
- struct {\r
- UINT32 instr:16; // 0:15 Pad (N) strength.\r
- UINT32 ipstr:16; // 16:31 Pad (P) strength.\r
- }r;\r
-} PAD_CONF1;\r
-\r
-typedef union{\r
- UINT32 dw;\r
- struct {\r
- UINT32 pad_val:1; // 0 These registers are implemented as dual read/write with dedicated storage each.\r
- UINT32 ioutenb:1; // 1 output enable\r
- UINT32 iinenb:1; // 2 input enable\r
- UINT32 Reserved:29; // 3:31 Reserved\r
- }r;\r
-} PAD_VAL;\r
-\r
-typedef union{\r
- UINT32 GPI;\r
- struct {\r
- UINT32 ihbpen:1; // 0 Pad high by pass enable\r
- UINT32 ihbpinen:1; // 1 Pad high by pass input\r
- UINT32 instaticen:1; // 2 TBD\r
- UINT32 ipstaticen:1; // 3 TBD\r
- UINT32 Overide_strap_pin :1; // 4 DFX indicates if it wants to override the strap pin value on this pad, if exists.\r
- UINT32 Overide_strap_pin_val:1; // 5 In case DFX need to override strap pin value and it exist for the specific pad, this value will be used.\r
- UINT32 TestMode_Pin_Mux:3; // 6:9 DFX Pin Muxing\r
- }r;\r
-} PAD_DFT;\r
-\r
-//\r
-// GPIO_USAGE value need to matche the PAD_VAL input/output enable bits.\r
-//\r
-typedef enum {\r
- Native = 0xFF, // Native, no need to set PAD_VALUE\r
- GPI = 2, // GPI, input only in PAD_VALUE\r
- GPO = 4, // GPO, output only in PAD_VALUE\r
- GPIO = 0, // GPIO, input & output\r
- TRISTS = 6, // Tri-State\r
- GPIO_NONE\r
-} GPIO_USAGE;\r
-\r
-typedef enum {\r
- LO = 0,\r
- HI = 1,\r
- NA = 0xFF\r
-} GPO_D4;\r
-\r
-typedef enum {\r
- F0 = 0,\r
- F1 = 1,\r
- F2 = 2,\r
- F3 = 3,\r
- F4 = 4,\r
- F5 = 5,\r
- F6 = 6,\r
- F7 = 7\r
-} GPIO_FUNC_NUM;\r
-\r
-//\r
-// Mapping to CONF0 bit 27:24\r
-// Note: Assume "Direct Irq En" is not set, unless specially notified.\r
-//\r
-typedef enum {\r
- TRIG_ = 0,\r
- TRIG_Edge_High = /*BIT3 |*/ BIT1, // Positive Edge (Rasing)\r
- TRIG_Edge_Low = /*BIT3 |*/ BIT2, // Negative Edge (Falling)\r
- TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1, // Both Edge\r
- TRIG_Level_High= /*BIT3 |*/ BIT1 | BIT0, // Level High\r
- TRIG_Level_Low = /*BIT3 |*/ BIT2 | BIT0, // Level Low\r
-} INT_TYPE;\r
-\r
-typedef enum {\r
- P_20K_H, // Pull Up 20K\r
- P_20K_L, // Pull Down 20K\r
- P_10K_H, // Pull Up 10K\r
- P_10K_L, // Pull Down 10K\r
- P_2K_H, // Pull Up 2K\r
- P_2K_L, // Pull Down 2K\r
- P_NONE // Pull None\r
-} PULL_TYPE;\r
-\r
-#ifdef EFI_DEBUG\r
- #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}\r
-#else\r
- #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) { usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}\r
-#endif\r
-\r
-//\r
-// GPIO CONF & PAD Initialization Data Structure for BayLake GPIOs bits.\r
-// NC = NCORE, SC = SCORE, SS= SSUS\r
-//\r
-typedef struct {\r
-\r
-#ifdef EFI_DEBUG\r
- char pad_name[32];// GPIO Pin Name for debug purpose\r
-#endif\r
-\r
- GPIO_USAGE usage; // GPIO pin used as Native mode or GPI/GPO/GPIO mode\r
- GPO_D4 gpod4; // GPO default value\r
- GPIO_FUNC_NUM func; // Function Number (F0~F7)\r
- INT_TYPE int_type; // Edge or Level trigger, low or high active\r
- PULL_TYPE pull; // Pull Up or Down\r
- UINT8 offset; // Equal with (PCONF0 register offset >> 4 bits)\r
-} GPIO_CONF_PAD_INIT;\r
-\r
-//\r
-//typedef UINT64 BOARD_FEATURES\r
-//\r
-typedef struct _EFI_PLATFORM_INFO_HOB {\r
- UINT16 PlatformType; // Platform Type\r
- UINT8 BoardId; // Board ID\r
- UINT8 BoardRev; // Board Revision\r
- PLATFORM_FLAVOR PlatformFlavor; // Platform Flavor\r
- UINT8 DDRDaughterCardCh0Id;// DDR daughter card channel 0 id\r
- UINT8 DDRDaughterCardCh1Id;// DDR daughter card channel 1 id\r
- UINT8 ECOId; // ECO applied on platform\r
- UINT16 IohSku;\r
- UINT8 IohRevision;\r
- UINT16 IchSku;\r
- UINT8 IchRevision;\r
- EFI_PLATFORM_PCI_DATA PciData;\r
- EFI_PLATFORM_CPU_DATA CpuData;\r
- EFI_PLATFORM_MEM_DATA MemData;\r
- EFI_PLATFORM_SYS_DATA SysData;\r
- EFI_PLATFORM_IGD_DATA IgdData;\r
- UINT8 RevisonId; // Structure Revision ID\r
- EFI_PHYSICAL_ADDRESS PlatformCfioData;\r
- EFI_PHYSICAL_ADDRESS PlatformGpioData_NC;\r
- EFI_PHYSICAL_ADDRESS PlatformGpioData_SC;\r
- EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS;\r
- EFI_PHYSICAL_ADDRESS PlatformGpioData_NC_TRI;\r
- EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_TRI;\r
- EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_TRI;\r
- EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1;\r
- EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_PR1_1;\r
- EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1_1;\r
-\r
- UINT8 CfioEnabled;\r
- UINT32 SsidSvid;\r
- UINT16 AudioSubsystemDeviceId;\r
- UINT64 AcpiOemId;\r
- UINT64 AcpiOemTableId;\r
- UINT16 MemCfgID;\r
-} EFI_PLATFORM_INFO_HOB;\r
-\r
-#pragma pack()\r
-\r
-EFI_STATUS\r
-GetPlatformInfoHob (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob\r
- );\r
-\r
-\r
-EFI_STATUS\r
-InstallPlatformClocksNotify (\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
- );\r
-\r
-EFI_STATUS\r
-InstallPlatformSysCtrlGPIONotify (\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
- );\r
-\r
-#endif\r