+++ /dev/null
-/** @file\r
- Register Definitions for I2C Driver/PEIM.\r
- \r
- Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>\r
- \r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
- \r
---*/\r
-\r
-#ifndef I2C_REGS_H\r
-#define I2C_REGS_H\r
-\r
-//\r
-// FIFO write delay value.\r
-//\r
-#define FIFO_WRITE_DELAY 2\r
-\r
-//\r
-// MMIO Register Definitions.\r
-//\r
-#define R_IC_CON ( 0x00) // I2C Control \r
-#define B_IC_RESTART_EN BIT5\r
-#define B_IC_SLAVE_DISABLE BIT6\r
-#define V_SPEED_STANDARD 0x02\r
-#define V_SPEED_FAST 0x04\r
-#define V_SPEED_HIGH 0x06\r
-#define B_MASTER_MODE BIT0\r
-\r
-#define R_IC_TAR ( 0x04) // I2C Target Address\r
-#define IC_TAR_10BITADDR_MASTER BIT12\r
-\r
-#define R_IC_SAR ( 0x08) // I2C Slave Address\r
-#define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address\r
-#define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command\r
-\r
-#define B_READ_CMD BIT8 // 1 = read, 0 = write\r
-#define B_CMD_STOP BIT9 // 1 = STOP\r
-#define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN\r
-\r
-#define V_WRITE_CMD_MASK ( 0xFF)\r
-\r
-#define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count\r
-#define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count\r
-#define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count\r
-#define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count\r
-#define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count\r
-#define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count\r
-#define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status\r
-#define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask\r
-#define I2C_INTR_GEN_CALL BIT11 // General call received\r
-#define I2C_INTR_START_DET BIT10\r
-#define I2C_INTR_STOP_DET BIT9\r
-#define I2C_INTR_ACTIVITY BIT8\r
-#define I2C_INTR_TX_ABRT BIT6 // Set on NACK\r
-#define I2C_INTR_TX_EMPTY BIT4\r
-#define I2C_INTR_TX_OVER BIT3\r
-#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold\r
-#define I2C_INTR_RX_OVER BIT1\r
-#define I2C_INTR_RX_UNDER BIT0\r
-#define R_IC_RawIntrStat ( 0x34) // I2C Raw Interrupt Status\r
-#define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold\r
-#define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold\r
-#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts\r
-#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt\r
-#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt\r
-#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt\r
-#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt\r
-#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt\r
-#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt\r
-#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt\r
-#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt\r
-#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt\r
-#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt\r
-#define R_IC_ENABLE ( 0x6C) // I2C Enable\r
-#define R_IC_STATUS ( 0x70) // I2C Status\r
-\r
-#define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits\r
-\r
-#define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.\r
-#define STAT_RFF BIT4 // RX FIFO is completely full\r
-#define STAT_RFNE BIT3 // RX FIFO is not empty\r
-#define STAT_TFE BIT2 // TX FIFO is completely empty\r
-#define STAT_TFNF BIT1 // TX FIFO is not full\r
-\r
-#define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register\r
-#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register\r
-#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register\r
-#define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register\r
-#define R_IC_DMA_CR ( 0x88) // DMA Control Register\r
-#define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level\r
-#define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level\r
-#define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register\r
-#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register\r
-#define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register\r
-#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register\r
-#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID\r
-#define R_IC_COMP_TYPE ( 0xFC) // Component Type\r
-\r
-#define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD\r
-#define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4\r
-#define I2C_FS_SCL_HCNT_VALUE_100M 0x54\r
-#define I2C_FS_SCL_LCNT_VALUE_100M 0x9a\r
-#define I2C_HS_SCL_HCNT_VALUE_100M 0x7\r
-#define I2C_HS_SCL_LCNT_VALUE_100M 0xE\r
-\r
-#define IC_TAR_10BITADDR_MASTER BIT12\r
-#define FIFO_SIZE 32\r
-#define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status\r
-#define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask\r
-#define I2C_INTR_GEN_CALL BIT11 // General call received\r
-#define I2C_INTR_START_DET BIT10\r
-#define I2C_INTR_STOP_DET BIT9\r
-#define I2C_INTR_ACTIVITY BIT8\r
-#define I2C_INTR_TX_ABRT BIT6 // Set on NACK\r
-#define I2C_INTR_TX_EMPTY BIT4\r
-#define I2C_INTR_TX_OVER BIT3\r
-#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold\r
-#define I2C_INTR_RX_OVER BIT1\r
-#define I2C_INTR_RX_UNDER BIT0\r
-\r
-#define R_PCH_LPIO_I2C_MEM_RESETS 0x804 // Software Reset\r
-#define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset\r
-#define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset\r
-#define R_PCH_LPSS_I2C_MEM_PCP 0x800 // Private Clock Parameters\r
-\r
-#endif
\ No newline at end of file
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