+++ /dev/null
-/** @file\r
- Gpio setting for multiplatform..\r
-\r
- Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
- \r\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- \r\r
-\r
-**/\r
-\r
-#include <BoardGpios.h>\r
-#include <Guid/SetupVariable.h>\r
-\r
-//\r
-//AlpineValley platform ocde begin\r
-//\r
-#define AV_SC_REG_GPIOS_MUXES_SEL0 0x48\r
-#define AV_SC_REG_GPIOS_MUXES_SEL1 0x4C\r
-#define AV_SC_REG_GPIOS_MUXES_SEL2 0x50\r
-#define AV_SC_REG_GPIOS_MUXES_EN0 0x54\r
-#define AV_SC_REG_GPIOS_MUXES_EN1 0x58\r
-#define AV_SC_REG_GPIOS_MUXES_EN2 0x5C\r
-//\r
-//AlpineValley platform code end\r
-//\r
-\r
-EFI_GUID gPeiSmbusPpiGuid = EFI_PEI_SMBUS_PPI_GUID;\r
-\r
-/**\r
- @param None\r
-\r
- @retval EFI_SUCCESS The function completed successfully.\r
-\r
-**/\r
-EFI_STATUS\r
-ConfigurePlatformSysCtrlGpio (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
- IN VOID *SmbusPpi\r
- )\r
-{\r
- //\r
- //AlpineValley platform code begin\r
- //\r
- // Initialize GPIO Settings:\r
- //\r
- UINT32 Status;\r
- EFI_PLATFORM_INFO_HOB *PlatformInfoHob;\r
-\r
- DEBUG ((EFI_D_INFO, "ConfigurePlatformSysCtrlGpio()...\n"));\r
-\r
- //\r
- // Obtain Platform Info from HOB.\r
- //\r
- Status = GetPlatformInfoHob ((const EFI_PEI_SERVICES **)PeiServices, &PlatformInfoHob);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // The GPIO settings are dependent upon the platform. Obtain the Board ID through\r
- // the EC to determine the current platform.\r
- //\r
- DEBUG ((EFI_D_INFO, "Platform Flavor | Board ID = 0x%X | 0x%X\n", PlatformInfoHob->PlatformFlavor, PlatformInfoHob->BoardId));\r
-\r
-\r
-\r
- Status = (**PeiServices).LocatePpi (\r
- (const EFI_PEI_SERVICES **)PeiServices,\r
- &gPeiSmbusPpiGuid,\r
- 0,\r
- NULL,\r
- (void **)&SmbusPpi\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // Select/modify the GPIO initialization data based on the Board ID.\r
- //\r
- switch (PlatformInfoHob->BoardId)\r
- {\r
- default:\r
- Status = EFI_SUCCESS;\r
-\r
- //\r
- // Do nothing for other RVP boards.\r
- //\r
- break;\r
- }\r
- return Status;\r
-}\r
-\r
-static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {\r
- {\r
- EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
- &gEfiPeiSmbusPpiGuid,\r
- ConfigurePlatformSysCtrlGpio\r
- }\r
-};\r
-\r
-EFI_STATUS\r
-InstallPlatformSysCtrlGPIONotify (\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- DEBUG ((EFI_D_INFO, "InstallPlatformSysCtrlGPIONotify()...\n"));\r
-\r
- Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);\r
- ASSERT_EFI_ERROR (Status);\r
- return EFI_SUCCESS;\r
-\r
-}\r
-\r
-#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable\r
-\r
-/**\r
- Returns the Correct GPIO table for Mobile/Desktop respectively.\r
- Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.\r
-\r
- @param PeiServices General purpose services available to every PEIM.\r
- @param PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor specified.\r
- @param BoardId BoardId ID as determined through the EC.\r
-\r
- @retval EFI_SUCCESS The function completed successfully.\r
- @retval EFI_DEVICE_ERROR KSC fails to respond.\r
-\r
-**/\r
-EFI_STATUS\r
-MultiPlatformGpioTableInit (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;\r
- UINTN VarSize;\r
- SYSTEM_CONFIGURATION SystemConfiguration;\r
-\r
- DEBUG ((EFI_D_INFO, "MultiPlatformGpioTableInit()...\n"));\r
-\r
- //\r
- // Select/modify the GPIO initialization data based on the Board ID.\r
- //\r
- switch (PlatformInfoHob->BoardId) {\r
-\r
- case BOARD_ID_MINNOW2: // Minnow2\r
- case BOARD_ID_MINNOW2_TURBOT: \r
- Status = (**PeiServices).LocatePpi (\r
- PeiServices,\r
- &gEfiPeiReadOnlyVariable2PpiGuid,\r
- 0,\r
- NULL,\r
- (void **)&PeiReadOnlyVarPpi\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
- \r
- VarSize = sizeof (SYSTEM_CONFIGURATION);\r
- Status = PeiReadOnlyVarPpi->GetVariable ( \r
- PeiReadOnlyVarPpi, \r
- PLATFORM_SETUP_VARIABLE_NAME, \r
- &gEfiSetupVariableGuid,\r
- NULL,\r
- &VarSize,\r
- &SystemConfiguration\r
- );\r
- \r
- if (SystemConfiguration.GpioWakeCapability == 1) {\r
- PlatformInfoHob->PlatformCfioData = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData2;\r
- }\r
- else {\r
- PlatformInfoHob->PlatformCfioData = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData;\r
- } \r
- \r
- PlatformInfoHob->PlatformGpioData_NC = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_NC[0];\r
- PlatformInfoHob->PlatformGpioData_SC = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SC[0];\r
- PlatformInfoHob->PlatformGpioData_SUS = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SUS[0];\r
- break;\r
-\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-UINT32\r
-GPIORead32 (\r
- IN UINT32 mmio_conf\r
- )\r
-{\r
- UINT32 conf_val;\r
- UINT32 i;\r
- conf_val = MmioRead32(mmio_conf);\r
- for(i=0;i<5;i++){\r
- if(conf_val == 0xffffffff)\r
- conf_val = MmioRead32(mmio_conf);\r
- else\r
- break;\r
- }\r
-\r
- return conf_val;\r
-}\r
-\r
-/**\r
-\r
- Set GPIO CONF0 and PAD_VAL registers for NC/SC/SUS GPIO clusters\r
-\r
- @param Gpio_Mmio_Offset GPIO_SCORE_OFFSET or GPIO_NCORE_OFFSET or GPIO_SSUS_OFFSET.\r
- @param Gpio_Pin_Num Pin numbers to config for each GPIO clusters.\r
- @param Gpio_Conf_Data GPIO_CONF_PAD_INIT data array for each GPIO clusters.\r
-\r
-**/\r
-VOID\r
-InternalGpioConfig (\r
- IN UINT32 Gpio_Mmio_Offset,\r
- IN UINT32 Gpio_Pin_Num,\r
- GPIO_CONF_PAD_INIT* Gpio_Conf_Data\r
- )\r
-{\r
- UINT32 index;\r
- UINT32 mmio_conf0;\r
- UINT32 mmio_padval;\r
- PAD_CONF0 conf0_val;\r
- PAD_VAL pad_val;\r
-\r
- //\r
- // GPIO WELL -- Memory base registers\r
- //\r
-\r
- // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
- // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900\r
- //\r
- for(index=0; index < Gpio_Pin_Num; index++)\r
- {\r
- //\r
- // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.\r
- //\r
- mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;\r
- mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;\r
-\r
-#ifdef EFI_DEBUG\r
- DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));\r
-\r
-#endif\r
- DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",\r
- Gpio_Conf_Data[index].usage,\r
- Gpio_Conf_Data[index].func,\r
- Gpio_Conf_Data[index].int_type,\r
- Gpio_Conf_Data[index].pull,\r
- mmio_conf0));\r
-\r
- //\r
- // Step 1: PadVal Programming.\r
- //\r
- pad_val.dw = GPIORead32(mmio_padval);\r
-\r
- //\r
- // Config PAD_VAL only for GPIO (Non-Native) Pin\r
- //\r
- if(Native != Gpio_Conf_Data[index].usage)\r
- {\r
- pad_val.dw &= ~0x6; // Clear bits 1:2\r
- pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal\r
-\r
- //\r
- // set GPO default value\r
- //\r
- if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)\r
- {\r
- pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;\r
- }\r
- }\r
-\r
-\r
- DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));\r
-\r
- MmioWrite32(mmio_padval, pad_val.dw);\r
-\r
- //\r
- // Step 2: CONF0 Programming\r
- // Read GPIO default CONF0 value, which is assumed to be default value after reset.\r
- //\r
- conf0_val.dw = GPIORead32(mmio_conf0);\r
-\r
- //\r
- // Set Function #\r
- //\r
- conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;\r
-\r
- if(GPO == Gpio_Conf_Data[index].usage)\r
- {\r
- //\r
- // If used as GPO, then internal pull need to be disabled.\r
- //\r
- conf0_val.r.Pull_assign = 0; // Non-pull\r
- }\r
- else\r
- {\r
- //\r
- // Set PullUp / PullDown\r
- //\r
- if(P_20K_H == Gpio_Conf_Data[index].pull)\r
- {\r
- conf0_val.r.Pull_assign = 0x1; // PullUp\r
- conf0_val.r.Pull_strength = 0x2;// 20K\r
- }\r
- else if(P_20K_L == Gpio_Conf_Data[index].pull)\r
- {\r
- conf0_val.r.Pull_assign = 0x2; // PullDown\r
- conf0_val.r.Pull_strength = 0x2;// 20K\r
- }\r
- else if(P_10K_H == Gpio_Conf_Data[index].pull)\r
- {\r
- conf0_val.r.Pull_assign = 0x1; // PullUp\r
- conf0_val.r.Pull_strength = 0x1;// 10K\r
- }\r
- else if(P_10K_L == Gpio_Conf_Data[index].pull)\r
- {\r
- conf0_val.r.Pull_assign = 0x2; // PullDown\r
- conf0_val.r.Pull_strength = 0x1;// 10K\r
- }\r
- else if(P_2K_H == Gpio_Conf_Data[index].pull)\r
- {\r
- conf0_val.r.Pull_assign = 0x1; // PullUp\r
- conf0_val.r.Pull_strength = 0x0;// 2K\r
- }\r
- else if(P_2K_L == Gpio_Conf_Data[index].pull)\r
- {\r
- conf0_val.r.Pull_assign = 0x2; // PullDown\r
- conf0_val.r.Pull_strength = 0x0;// 2K\r
- }\r
- else if(P_NONE == Gpio_Conf_Data[index].pull)\r
- {\r
- conf0_val.r.Pull_assign = 0; // Non-pull\r
- }\r
- else\r
- {\r
- ASSERT(FALSE); // Invalid value\r
- }\r
- }\r
-\r
-\r
- //\r
- // Set INT Trigger Type\r
- //\r
- conf0_val.dw &= ~0x0f000000; // Clear bits 27:24\r
-\r
- //\r
- // Set INT Trigger Type\r
- //\r
- if(TRIG_ == Gpio_Conf_Data[index].int_type)\r
- {\r
- //\r
- // Interrupt not capable, clear bits 27:24\r
- //\r
- }\r
- else\r
- {\r
- conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;\r
- }\r
-\r
- DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));\r
-\r
- //\r
- // Write back the targeted GPIO config value according to platform (board) GPIO setting.\r
- //\r
- MmioWrite32 (mmio_conf0, conf0_val.dw);\r
- }\r
-\r
- //\r
- // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
- // GPIO SCORE write 0x01001002 to IOBASE + 0x0900\r
- //\r
-}\r
-\r
-/**\r
- Returns the Correct GPIO table for Mobile/Desktop respectively.\r
- Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.\r
-\r
- @param PeiServices General purpose services available to every PEIM.\r
- @param PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor specified.\r
- @param BoardId BoardId ID as determined through the EC.\r
-\r
- @retval EFI_SUCCESS The function completed successfully.\r
- @retval EFI_DEVICE_ERROR KSC fails to respond.\r
-\r
-**/\r
-EFI_STATUS\r
-MultiPlatformGpioProgram (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
- )\r
-{\r
-#if !_SIMIC_\r
- CFIO_INIT_STRUCT* PlatformCfioDataPtr;\r
-\r
- PlatformCfioDataPtr = (CFIO_INIT_STRUCT *) (UINTN) PlatformInfoHob->PlatformCfioData;\r
- DEBUG ((EFI_D_INFO, "MultiPlatformGpioProgram()...\n"));\r
-\r
- //\r
- // SCORE GPIO WELL -- IO base registers\r
- //\r
-\r
- //\r
- // GPIO_USE_SEL Register -> 1 = GPIO 0 = Native\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL, PlatformCfioDataPtr->Use_Sel_SC0);\r
-\r
- //\r
- // Set GP_LVL Register\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL , PlatformCfioDataPtr->GP_Lvl_SC0);\r
-\r
- //\r
- // GP_IO_SEL Register -> 1 = Input 0 = Output. If Native Mode don't care\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL, PlatformCfioDataPtr->Io_Sel_SC0);\r
-\r
- //\r
- // GPIO Triger Positive Edge Enable Register\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TPE, PlatformCfioDataPtr->TPE_SC0);\r
-\r
- //\r
- // GPIO Trigger Negative Edge Enable Register\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TNE, PlatformCfioDataPtr->TNE_SC0);\r
-\r
- //\r
- // GPIO Trigger Status\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TS, PlatformCfioDataPtr->TS_SC0);\r
-\r
- //\r
- // GPIO_USE_SEL2 Register -> 1 = GPIO 0 = Native\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL2, PlatformCfioDataPtr->Use_Sel_SC1);\r
-\r
- //\r
- // Set GP_LVL2 Register\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL2, PlatformCfioDataPtr->GP_Lvl_SC1);\r
-\r
- //\r
- // GP_IO_SEL2 Register -> 1 = Input 0 = Output. If Native Mode don't care\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL2, PlatformCfioDataPtr->Io_Sel_SC1);\r
-\r
- //\r
- // GPIO_USE_SEL3 Register -> 1 = GPIO 0 = Native\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL3, PlatformCfioDataPtr->Use_Sel_SC2);\r
-\r
- //\r
- // Set GP_LVL3 Register\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL3, PlatformCfioDataPtr->GP_Lvl_SC2);\r
-\r
- //\r
- // GP_IO_SEL3 Register -> 1 = Input 0 = Output if Native Mode don't care\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL3, PlatformCfioDataPtr->Io_Sel_SC2);\r
-\r
- //\r
- // SUS GPIO WELL -- IO base registers\r
- //\r
-\r
- //\r
- // GPIO_USE_SEL Register -> 1 = GPIO 0 = Native\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_USE_SEL, PlatformCfioDataPtr->Use_Sel_SS);\r
-\r
- //\r
- // Set GP_LVL Register\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_LVL , PlatformCfioDataPtr->GP_Lvl_SS);\r
-\r
- //\r
- // GP_IO_SEL Register -> 1 = Input 0 = Output. If Native Mode don't care.\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_IO_SEL, PlatformCfioDataPtr->Io_Sel_SS);\r
-\r
- //\r
- // GPIO Triger Positive Edge Enable Register.\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TPE, PlatformCfioDataPtr->TPE_SS);\r
-\r
- //\r
- // GPIO Trigger Negative Edge Enable Register.\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TNE, PlatformCfioDataPtr->TNE_SS);\r
-\r
- //\r
- // GPIO Trigger Status.\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TS, PlatformCfioDataPtr->TS_SS);\r
-\r
- //\r
- // GPIO Wake Enable.\r
- //\r
- IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_WAKE_EN, PlatformCfioDataPtr->WE_SS);\r
-\r
- //\r
- // Config SC/NC/SUS GPIO Pins\r
- //\r
- switch (PlatformInfoHob->BoardId) {\r
- case BOARD_ID_MINNOW2:\r
- case BOARD_ID_MINNOW2_TURBOT:\r
- DEBUG ((EFI_D_INFO, "Start to config Minnow2 GPIO pins\n"));\r
- InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mMinnow2_GpioInitData_SC)/sizeof(mMinnow2_GpioInitData_SC[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SC);\r
- InternalGpioConfig(GPIO_NCORE_OFFSET, sizeof(mMinnow2_GpioInitData_NC)/sizeof(mMinnow2_GpioInitData_NC[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_NC);\r
- InternalGpioConfig(GPIO_SSUS_OFFSET, sizeof(mMinnow2_GpioInitData_SUS)/sizeof(mMinnow2_GpioInitData_SUS[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SUS);\r
- break;\r
- default:\r
-\r
- break;\r
- }\r
-\r
- //\r
- // configure the CFIO Pnp settings\r
- //\r
- if (PlatformInfoHob->CfioEnabled) {\r
- if (PlatformInfoHob->BoardId == BOARD_ID_MINNOW2 || PlatformInfoHob->BoardId == BOARD_ID_MINNOW2_TURBOT){\r
- InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mNB_BB_FAB3_GpioInitData_SC_TRI)/sizeof(mNB_BB_FAB3_GpioInitData_SC_TRI[0]), (GPIO_CONF_PAD_INIT *) (UINTN)PlatformInfoHob->PlatformGpioData_SC_TRI);\r
- }\r
- }\r
-#else\r
- DEBUG ((EFI_D_INFO, "Skip MultiPlatformGpioProgram()...for SIMICS or HYB model\n"));\r
-#endif\r
- return EFI_SUCCESS;\r
-}\r
-\r
projects / mirror_edk2.git / blobdiff