+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
- \r\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- \r\r
-\r
-Module Name:\r
-\r
-\r
- ClockControl.c\r
-\r
-Abstract:\r
-\r
- Sets platform/SKU specific clock routing information.\r
-\r
-\r
-\r
---*/\r
-\r
-#include "PlatformDxe.h"\r
-#include <Protocol/CK505ClockPlatformInfo.h>\r
-\r
-//\r
-// Default clock routing informtion (All On)\r
-//\r
-EFI_CLOCK_PLATFORM_INFO mDefClockPolicy = {NULL, 0, NULL, 0, NULL, 0};\r
-\r
-//\r
-// Clock Settings\r
-//\r
-// Static clock table.\r
-// This should be used to define any clock settings that are static\r
-// (Always On or Always Off). Dynamic clocks should be set to enabled\r
-// in this table.\r
-//\r
-EFI_STATIC_SIGNALS mAtxStaticClocks[] = {\r
- {SrcClk8, Enabled, All},\r
- {SrcClk7, Enabled, All},\r
- {SrcClk6, Enabled, All},\r
- {SrcClk5, Enabled, All},\r
- {SrcClk4, Enabled, All},\r
- {SrcClk3, Enabled, All},\r
- {SrcClk2, Enabled, All},\r
- {SrcClk1, Enabled, All},\r
- {SrcClk0, Enabled, All},\r
- {Ref0, Enabled, All},\r
- {Dot96, Enabled, All},\r
- {Usb48, Enabled, All},\r
- {PciClkF5, Enabled, All},\r
- {PciClk0, Enabled, All},\r
- {PciClk2, Enabled, All},\r
- {PciClk3, Enabled, All},\r
- {PciClk4, Disabled, All},\r
- {Cr_B, EnabledWithSwitch, All},\r
-};\r
-\r
-//\r
-// ClockSxInfo Table\r
-// This is a list of clocks that need to be set to a known state when the\r
-// system enters S4 or S5.\r
-//\r
-EFI_STATIC_SIGNALS mAtxSxClocks[] = {\r
- {SaveClockConfiguration, Disabled, All}\r
-};\r
-\r
-//\r
-// ATX settings structure\r
-//\r
-EFI_CLOCK_PLATFORM_INFO mAtxClockSettings = {\r
- mAtxStaticClocks,\r
- sizeof(mAtxStaticClocks) / sizeof(mAtxStaticClocks[0]),\r
- mAtxSxClocks,\r
- sizeof(mAtxSxClocks) / sizeof(mAtxSxClocks[0])\r
-};\r
-\r
-#if defined( RVP_SUPPORT ) && RVP_SUPPORT\r
-//\r
-// RVP Clock Settings\r
-//\r
-// Static clock table.\r
-// This should be used to define any clock settings that are static\r
-// (Always On or Always Off). Dynamic clocks should be set to enabled\r
-// in this table.\r
-//\r
-//UPSD_TBD Check with Jan if any porting required.\r
-//\r
-EFI_STATIC_SIGNALS mRvpStaticClocks[] = {\r
- {SrcClk11, Enabled, All}, // Not used/not present but leave coding enabled\r
- {SrcClk10, Enabled, All}, // Not used/not present but leave coding enabled\r
- {SrcClk9, Enabled, All}, // Not used/not present but leave coding enabled\r
- {SrcClk8, Enabled, All}, // ICHSATAII\r
- {SrcClk7, Enabled, All}, // DPL_REFSSCLKIN\r
- {SrcClk6, Enabled, All}, // 100M_MCH\r
- {SrcClk5, Enabled, All}, // Mini-PCIe //TODO PNV: Need to check ICH GPIO38:\r
- // 0: turn on; 1: turn off\r
- {SrcClk4, Enabled, All}, // ICHSATA\r
- {SrcClk3, Enabled, All}, // 100M_ICH\r
- {SrcClk2, Enabled, All}, // 100M_LAN\r
- {SrcClk1, Enabled, All}, // 25M_LAN\r
- {SrcClk0, Enabled, All}, // 96M_DREF\r
- {Ref0, Enabled, All},\r
- {Dot96, Enabled, All},\r
- {Usb48, Enabled, All},\r
- {PciClkF5, Enabled, All}, // 33M_ICH\r
- {PciClk0, Enabled, All}, // 33M_RISER\r
- {PciClk1, Enabled, All}, // 33M_RISER\r
- {PciClk2, Enabled, All}, // VDD_Clock\r
- {PciClk3, Enabled, All}, // 33M_S1\r
- {PciClk4, Enabled, All}, // 33M_PA\r
-};\r
-\r
-//\r
-// Dynamic clock table\r
-// This is used to determine if a clock should be left on or turned off based\r
-// on the presence of a device. The bridge information is used so the bus\r
-// number for the device to be detected can be found.\r
-//\r
-\r
-//\r
-// ClockSxInfo Table\r
-// This is a list of clocks that need to be set to a known state when the\r
-// system enters S4 or S5.\r
-//\r
-EFI_STATIC_SIGNALS mRvpSxClocks[] = {\r
- {SaveClockConfiguration, Disabled, All}\r
-};\r
-\r
-//\r
-// RVP settings structure\r
-//\r
-EFI_CLOCK_PLATFORM_INFO mRvpClockSettings = {\r
- mRvpStaticClocks,\r
- sizeof(mRvpStaticClocks) / sizeof(mRvpStaticClocks[0]),\r
- 0, // No clocks will be turned off mRvpDynamicClocks,\r
- 0, // No clocks will be turned off sizeof(mRvpDynamicClocks) / sizeof(mRvpDynamicClocks[0]),\r
- mRvpSxClocks,\r
- sizeof(mRvpSxClocks) / sizeof(mRvpSxClocks[0])\r
-};\r
-#endif\r
-\r
-VOID\r
-InitializeClockRouting(\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINTN BoardIdVarSize;\r
- EFI_BOARD_FEATURES BoardIdVar;\r
- EFI_CLOCK_PLATFORM_INFO *ClockPolicy;\r
- EFI_HANDLE Handle;\r
-\r
- ClockPolicy = &mDefClockPolicy;\r
-\r
- //\r
- // Do modifications based on board type\r
- //\r
- BoardIdVarSize = sizeof (EFI_BOARD_FEATURES);\r
- Status = gRT->GetVariable (\r
- BOARD_FEATURES_NAME,\r
- &gEfiBoardFeaturesGuid,\r
- NULL,\r
- &BoardIdVarSize,\r
- &BoardIdVar\r
- );\r
- if (!EFI_ERROR (Status)) {\r
-\r
-#if defined( RVP_SUPPORT ) && RVP_SUPPORT\r
- if (BoardIdVar & B_BOARD_FEATURES_RVP) {\r
- ClockPolicy = &mRvpClockSettings;\r
- }\r
-#else\r
-\r
- //\r
- // Isolate board type information\r
- //\r
- BoardIdVar = BoardIdVar & (B_BOARD_FEATURES_FORM_FACTOR_ATX |\r
- B_BOARD_FEATURES_FORM_FACTOR_BTX |\r
- B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX |\r
- B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX);\r
-\r
- if (BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_ATX ||\r
- BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX) {\r
- ClockPolicy = &mAtxClockSettings;\r
- }\r
-\r
-#endif\r
-\r
- }\r
-\r
- Handle = NULL;\r
- Status = gBS->InstallProtocolInterface (\r
- &Handle,\r
- &gEfiCk505ClockPlatformInfoGuid,\r
- EFI_NATIVE_INTERFACE,\r
- ClockPolicy\r
- );\r
- ASSERT_EFI_ERROR(Status);\r
-\r
-}\r
-\r
-\r
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