+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
- \r\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- \r\r
-\r
-Module Name:\r
-\r
-\r
- IchRegTable.c\r
-\r
-Abstract:\r
-\r
- Register initialization table for Ich.\r
-\r
-\r
-\r
---*/\r
-\r
-#include <Library/EfiRegTableLib.h>\r
-#include "PlatformDxe.h"\r
-extern EFI_PLATFORM_INFO_HOB mPlatformInfo;\r
-\r
-#define R_EFI_PCI_SVID 0x2C\r
-\r
-EFI_REG_TABLE mSubsystemIdRegs [] = {\r
-\r
- //\r
- // Program SVID and SID for PCI devices.\r
- // Combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE in order to boost performance\r
- //\r
- PCI_WRITE (\r
- MC_BUS, MC_DEV, MC_FUN, R_EFI_PCI_SVID, EfiPciWidthUint32,\r
- V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
- ),\r
-\r
- PCI_WRITE (\r
- IGD_BUS, IGD_DEV, IGD_FUN_0, R_EFI_PCI_SVID, EfiPciWidthUint32,\r
- V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
- ),\r
-\r
- PCI_WRITE(\r
- DEFAULT_PCI_BUS_NUMBER_PCH, 0, 0, R_EFI_PCI_SVID, EfiPciWidthUint32,\r
- V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
- ),\r
- PCI_WRITE (\r
- DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, R_PCH_LPC_SS, EfiPciWidthUint32,\r
- V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
- ),\r
- PCI_WRITE (\r
- DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, R_PCH_SATA_SS, EfiPciWidthUint32,\r
- V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
- ),\r
- PCI_WRITE (\r
- DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SMBUS, PCI_FUNCTION_NUMBER_PCH_SMBUS, R_PCH_SMBUS_SVID, EfiPciWidthUint32,\r
- V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
- ),\r
- PCI_WRITE (\r
- DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_USB, PCI_FUNCTION_NUMBER_PCH_EHCI, R_PCH_EHCI_SVID, EfiPciWidthUint32,\r
- V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
- ),\r
- PCI_WRITE (\r
- DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, R_PCH_PCIE_SVID, EfiPciWidthUint32,\r
- V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
- ),\r
- PCI_WRITE (\r
- DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, R_PCH_PCIE_SVID, EfiPciWidthUint32,\r
- V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
- ),\r
- PCI_WRITE (\r
- DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, R_PCH_PCIE_SVID, EfiPciWidthUint32,\r
- V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
- ),\r
- PCI_WRITE (\r
- DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, R_PCH_PCIE_SVID, EfiPciWidthUint32,\r
- V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
- ),\r
- TERMINATE_TABLE\r
-};\r
-\r
-/**\r
- Updates the mSubsystemIdRegs table, and processes it. This should program\r
- the Subsystem Vendor and Device IDs.\r
-\r
- @retval Returns VOID\r
-\r
-**/\r
-VOID\r
-InitializeSubsystemIds (\r
- )\r
-{\r
-\r
- EFI_REG_TABLE *RegTablePtr;\r
- UINT32 SubsystemVidDid;\r
-\r
- SubsystemVidDid = mPlatformInfo.SsidSvid;\r
-\r
- RegTablePtr = mSubsystemIdRegs;\r
-\r
- //\r
- // While we are not at the end of the table\r
- //\r
- while (RegTablePtr->Generic.OpCode != OP_TERMINATE_TABLE) {\r
- //\r
- // If the data to write is the original SSID\r
- //\r
- if (RegTablePtr->PciWrite.Data ==\r
- ((V_PCH_DEFAULT_SID << 16) |\r
- V_PCH_INTEL_VENDOR_ID)\r
- ) {\r
-\r
- //\r
- // Then overwrite it to use the alternate SSID\r
- //\r
- RegTablePtr->PciWrite.Data = SubsystemVidDid;\r
- }\r
-\r
- //\r
- // Go to next table entry\r
- //\r
- RegTablePtr++;\r
- }\r
-\r
- RegTablePtr = mSubsystemIdRegs;\r
-\r
-\r
- //\r
- // Program the SSVID/SSDID\r
- //\r
- ProcessRegTablePci (mSubsystemIdRegs, mPciRootBridgeIo, NULL);\r
-\r
-}\r