+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
- \r\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- \r\r
-\r
-\r
-Module Name:\r
-\r
- IchS3Save.c\r
-\r
-Abstract:\r
-\r
- SMM S3 handler Driver implementation file\r
-\r
-Revision History\r
-\r
-**/\r
-#include "SmmPlatform.h"\r
-\r
-extern UINT16 mAcpiBaseAddr;\r
-EFI_PHYSICAL_ADDRESS mRuntimeScriptTableBase;\r
-\r
-EFI_STATUS\r
-InitRuntimeScriptTable (\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT32 VarAttrib;\r
- UINTN VarSize;\r
- ACPI_VARIABLE_SET_COMPATIBILITY *AcpiVariableBase;\r
-\r
- //\r
- // Allocate runtime ACPI script table space. We need it to save some\r
- // settings done by CSM, which runs after normal script table closed\r
- //\r
- Status = gBS->AllocatePages (\r
- AllocateAnyPages,\r
- EfiACPIReclaimMemory,\r
- 1,\r
- &mRuntimeScriptTableBase\r
- );\r
- if (EFI_ERROR(Status)) {\r
- return EFI_OUT_OF_RESOURCES ;\r
- }\r
-\r
- //\r
- // Save runtime script table base into global ACPI variable\r
- //\r
- VarAttrib = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS\r
- | EFI_VARIABLE_NON_VOLATILE;\r
- VarSize = sizeof (UINTN);\r
- Status = SystemTable->RuntimeServices->GetVariable (\r
- ACPI_GLOBAL_VARIABLE,\r
- &gEfiAcpiVariableCompatiblityGuid,\r
- &VarAttrib,\r
- &VarSize,\r
- &AcpiVariableBase\r
- );\r
- if (EFI_ERROR(Status)) {\r
- return Status;\r
- }\r
-\r
- AcpiVariableBase->RuntimeScriptTableBase = mRuntimeScriptTableBase;\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-SaveRuntimeScriptTable (\r
- VOID\r
- )\r
-{\r
- SMM_PCI_IO_ADDRESS PciAddress;\r
- UINT32 Data32;\r
- UINT16 Data16;\r
- UINT8 Data8;\r
- UINT8 Mask;\r
- UINTN Index;\r
- UINTN Offset;\r
- UINT8 RegTable[] = {\r
-\r
- //\r
- //Bus , Dev, Func, DMI\r
- //\r
- 0x00 , 0x00, 0x00,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0x00 , 0x08, 0x00, 0x00, 0x30, 0x00, 0x00, 0xa0,\r
-\r
- //\r
- //Bus , Dev, Func, LPC device\r
- //\r
- 0x00 , 0x1F, 0x00,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0x00 , 0x08, 0x00, 0x07, 0x00, 0x00, 0x90, 0x00,\r
-\r
- //\r
- //Bus , Dev, Func, PCIE device\r
- //\r
- 0x00 , 0x1C, 0x00,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0xC0 , 0x83, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,\r
-\r
- //\r
- //Bus , Dev, Func, PCIE device\r
- //\r
- 0x00 , 0x1C, 0x00,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0x03 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
-\r
- //\r
- //Bus , Dev, Func, SATA device\r
- //\r
- 0x00 , 0x13, 0x00,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0xf4 , 0xab, 0x27, 0x10, 0xf1, 0x1d, 0x00, 0x40,\r
-\r
- //\r
- //Bus , Dev, Func, EHCI device\r
- //\r
- 0x00 , 0x1D, 0x00,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0x10 , 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,\r
-\r
- //\r
- //Bus , Dev, Func, SMBUS device\r
- //\r
- 0x00 , 0x1f, 0x03,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0x10 , 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
-\r
- //\r
- //Bus , Dev, Func, SMBUS device\r
- //\r
- 0x00 , 0x1f, 0x03,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
-\r
- //\r
- //Bus , Dev, Func, VGA bus1\r
- //\r
- 0x01 , 0x00, 0x00,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0x58 , 0x81, 0x18, 0x01, 0xb0, 0x00, 0x00, 0x00,\r
-\r
- //\r
- //Bus , Dev, Func, VGA bus1\r
- //\r
- 0x01 , 0x00, 0x00,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
-\r
- //\r
- //Bus , Dev, Func, VGA bus1 function 1\r
- //\r
- 0x01 , 0x00, 0x01,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0x51 , 0x80, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00,\r
-\r
- //\r
- //Bus , Dev, Func, VGA bus1 function 1\r
- //\r
- 0x01 , 0x00, 0x01,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
-\r
- //\r
- //Bus , Dev, Func, IGD bus0 function 0\r
- //\r
- 0x00 , 0x02, 0x00,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0x42 , 0x81, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,\r
-\r
- //\r
- //Bus , Dev, Func, USB bus0 function 0\r
- //\r
- 0x00 , 0x16, 0x00,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0x32 , 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
-\r
- //\r
- //Bus , Dev, Func, HD Audio bus0 function 0\r
- //\r
- 0x00 , 0x1B, 0x00,\r
-\r
- //\r
- //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
- //\r
- 0x00 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,\r
-\r
- //\r
- //0xFF indicates the end of the table\r
- //\r
- 0xFF\r
- };\r
-\r
- //\r
- // These registers have to set in byte order\r
- //\r
- UINT8 ExtReg[] = { 0x9E, 0x9D }; // SMRAM settings\r
-\r
-\r
-\r
- //\r
- // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM\r
- // and vital to S3 resume. That's why we put save code here\r
- //\r
- PciAddress.Bus = 0;\r
- PciAddress.Device = 0;\r
- PciAddress.Function = 0;\r
- PciAddress.ExtendedRegister = 0;\r
-\r
- for (Index = 0; Index < 2; Index++) {\r
- //\r
- // Read SRAM setting from Pci(0, 0, 0)\r
- //\r
- PciAddress.Register = ExtReg[Index];\r
- Data8 = MmioRead8 (\r
- MmPciAddress (0,\r
- PciAddress.Bus,\r
- PciAddress.Device,\r
- PciAddress.Function,\r
- PciAddress.Register\r
- )\r
- );\r
-\r
- //\r
- // Save latest settings to runtime script table\r
- //\r
- S3BootScriptSavePciCfgWrite(\r
- S3BootScriptWidthUint8,\r
- *(UINT64*)&PciAddress,\r
- 1,\r
- &Data8\r
- );\r
- }\r
-\r
-\r
- //\r
- // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM\r
- // and vital to S3 resume. That's why we put save code here\r
- //\r
- Index = 0;\r
- while (RegTable[Index] != 0xFF) {\r
-\r
- PciAddress.Bus = RegTable[Index++];\r
- PciAddress.Device = RegTable[Index++];\r
- PciAddress.Function = RegTable[Index++];\r
- PciAddress.Register = 0;\r
- PciAddress.ExtendedRegister = 0;\r
-\r
- Data16 = MmioRead16 (\r
- MmPciAddress (0,\r
- PciAddress.Bus,\r
- PciAddress.Device,\r
- PciAddress.Function,\r
- PciAddress.Register\r
- )\r
- );\r
-\r
- if (Data16 == 0xFFFF) {\r
- Index+=8;\r
- continue;\r
- }\r
-\r
- for (Offset = 0, Mask = 0x01; Offset < 256; Offset+=4, Mask<<=1) {\r
-\r
- if (Mask == 0x00) {\r
- Mask = 0x01;\r
- }\r
-\r
- if (RegTable[Index + Offset/32] & Mask ) {\r
-\r
- PciAddress.Register = (UINT8)Offset;\r
- Data32 = MmioRead32 (MmPciAddress (0, PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register));\r
-\r
- //\r
- // Save latest settings to runtime script table\r
- //\r
- S3BootScriptSavePciCfgWrite (\r
- S3BootScriptWidthUint32,\r
- *(UINT64*)&PciAddress,\r
- 1,\r
- &Data32\r
- );\r
- }\r
- }\r
-\r
- Index += 8;\r
-\r
- }\r
-\r
-\r
- //\r
- // Save I/O ports to S3 script table\r
- //\r
-\r
- //\r
- // Selftest KBC\r
- //\r
- Data8 = 0xAA;\r
- S3BootScriptSaveIoWrite (\r
- S3BootScriptWidthUint8,\r
- 0x64,\r
- (UINTN)1,\r
- &Data8\r
- );\r
-\r
- Data32 = IoRead32(mAcpiBaseAddr + R_PCH_SMI_EN);\r
-\r
- S3BootScriptSaveIoWrite (\r
- S3BootScriptWidthUint32,\r
- (mAcpiBaseAddr + R_PCH_SMI_EN),\r
- 1,\r
- &Data32\r
- );\r
-\r
- //\r
- // Save B_ICH_TCO_CNT_LOCK so it will be done on S3 resume path.\r
- //\r
- Data16 = IoRead16(mAcpiBaseAddr + R_PCH_TCO_CNT);\r
-\r
- S3BootScriptSaveIoWrite (\r
- S3BootScriptWidthUint16,\r
- mAcpiBaseAddr + R_PCH_TCO_CNT,\r
- 1,\r
- &Data16\r
- );\r
-\r
-\r
- return EFI_SUCCESS;\r
-}\r
projects / mirror_edk2.git / blobdiff