X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPkg%2FArmPkg.dec;h=473b077dd2998c52047ca168ceaa3ba5f1edaeca;hp=debe066b6f7b3503e209431d36a2643dcbe60a99;hb=d0def00d33fa5d4a70c427dfc9a36d826b42967d;hpb=4f2494cf534a323a7094f8c531f5b9ef51751cfb

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index debe066b6f..473b077dd2 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -41,6 +41,8 @@
   ArmGicArchLib|Include/Library/ArmGicArchLib.h
   ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h
   ArmSvcLib|Include/Library/ArmSvcLib.h
+  OpteeLib|Include/Library/OpteeLib.h
+  StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
 
 [Guids.common]
   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
@@ -57,6 +59,7 @@
   ## Arm System Control and Management Interface(SCMI) Clock management protocol
   ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
   gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
+  gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }
 
   ## Arm System Control and Management Interface(SCMI) Clock management protocol
   ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
@@ -78,13 +81,13 @@
   # it has been configured by the CPU DXE
   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
 
-  # Define if the spin-table mechanism is used by the secondary cores when booting
-  # Linux (instead of PSCI)
-  gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
-
   # Define if the GICv3 controller should use the GICv2 legacy
   gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
 
+  # Whether to implement warm reboot for capsule update using a jump back to the
+  # PEI entry point with caches and interrupts disabled.
+  gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F
+
 [PcdsFeatureFlag.ARM]
   # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
   # TRUE may be appropriate to fix performance problems if you don't care about
@@ -167,16 +170,6 @@
   # By default we do not do a transition to non-secure mode
   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 
-  # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
-  gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
-
-  # If the fixed FDT address is not available, then it should be loaded below the kernel.
-  # The recommendation from the Linux kernel is to have the FDT below 16KB.
-  # (see the kernel doc: Documentation/arm/Booting)
-  gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023
-  # The FDT blob must be loaded at a 64bit aligned address.
-  gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
-
   # Non Secure Access Control Register
   # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
   # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
@@ -215,12 +208,6 @@
   # Other modes include using SP0 or switching to Aarch32, but these are
   # not currently supported.
   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
-  # If the fixed FDT address is not available, then it should be loaded above the kernel.
-  # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.
-  # (see the kernel doc: Documentation/arm64/booting.txt)
-  gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023
-  # The FDT blob must be loaded at a 2MB aligned address.
-  gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026
 
 
 #
@@ -235,6 +222,9 @@
   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 
+  gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
+  gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
+
 [PcdsFixedAtBuild.common, PcdsDynamic.common]
   #
   # ARM Architectural Timer