X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPkg%2FDrivers%2FCpuDxe%2FAArch64%2FMmu.c;h=3e216c7cb235165b3df686aabff58628dd4ab801;hp=d8bb41978066334e8b88cd43b0df3051a9e717a2;hb=bdecff6c0f23027c643cce70ae2004420dc81324;hpb=c4149528d4603656fbddb21b5cba821cac90cbdb diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c index d8bb419780..3e216c7cb2 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -3,6 +3,7 @@ Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
Portions copyright (c) 2010, Apple Inc. All rights reserved.
Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.
+Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -203,28 +204,30 @@ EfiAttributeToArmAttribute ( switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) { case EFI_MEMORY_UC: - ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY; + if (ArmReadCurrentEL () == AARCH64_EL2) { + ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK; + } else { + ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK; + } break; case EFI_MEMORY_WC: ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE; break; case EFI_MEMORY_WT: - ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH; + ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE; break; case EFI_MEMORY_WB: - ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK; + ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; break; default: - DEBUG ((EFI_D_ERROR, "EfiAttributeToArmAttribute: 0x%lX attributes is not supported.\n", EfiAttributes)); - ASSERT (0); - ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY; + ArmAttributes = TT_ATTR_INDX_MASK; } // Set the access flag to match the block attributes ArmAttributes |= TT_AF; // Determine protection attributes - if (EfiAttributes & EFI_MEMORY_WP) { + if (EfiAttributes & EFI_MEMORY_RO) { ArmAttributes |= TT_AP_RO_RO; }