X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPkg%2FDrivers%2FPL390Gic%2FPL390GicNonSec.c;h=526af02d3ee23caa829f99545eff9beeea7dbf05;hp=9a9006f0a39511e86ec790d3cbcfa4847f0b8cee;hb=8e01b449de91cfcd1bdf473ae1bc766c22eb616e;hpb=58b5d037b4627460242c9333860faabf6115069e diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c index 9a9006f0a3..526af02d3e 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c @@ -21,11 +21,11 @@ EFIAPI PL390GicEnableInterruptInterface ( IN INTN GicInterruptInterfaceBase ) -{\s\s -\s\s/* -\s\s * Enable the CPU interface in Non-Secure world -\s\s * Note: The ICCICR register is banked when Security extensions are implemented\s\s -\s\s */ +{ + /* + * Enable the CPU interface in Non-Secure world + * Note: The ICCICR register is banked when Security extensions are implemented + */ MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,0x00000001); } @@ -50,7 +50,7 @@ PL390GicSendSgiTo ( IN INTN CPUTargetList ) { -\s\sMmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16)); + MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16)); } UINT32 @@ -65,9 +65,9 @@ PL390GicAcknowledgeSgiFrom ( InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID -\s\sif (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) { -\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR -\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); + if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) { + //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR + MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); return 1; } else { return 0; @@ -87,9 +87,9 @@ PL390GicAcknowledgeSgi2From ( InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID -\s\sif((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) { -\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR -\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); + if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) { + //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR + MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); return 1; } else { return 0;