X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPkg%2FDrivers%2FPL390Gic%2FPL390GicSec.c;fp=ArmPkg%2FDrivers%2FPL390Gic%2FPL390GicSec.c;h=bf4c010b7043a57ea71b67d3c79933e53f976e6a;hp=156e0601e8770e9ef08a37fc3d76f6ddf47e18fd;hb=9e2b420ee9602b82530ad5d6933098fc92ac1190;hpb=838725abd776c709d1033df137064c4f05d31b63

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
index 156e0601e8..bf4c010b70 100644
--- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
@@ -12,6 +12,7 @@
 *
 **/
 
+#include <Uefi.h>
 #include <Library/IoLib.h>
 #include <Drivers/PL390Gic.h>
 
@@ -26,28 +27,27 @@ PL390GicSetupNonSecure (
   IN  INTN          GicInterruptInterfaceBase
   )
 {
-   UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);
+  UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);
 
-   //Set priority Mask so that no interrupts get through to CPU
-   MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);
+  // Set priority Mask so that no interrupts get through to CPU
+  MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);
 
-   //Check if there are any pending interrupts
-   while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF))
-   {
-     //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
-     UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
+  // Check if there are any pending interrupts
+  while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) {
+    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
+    UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
 
-     //Write to End of interrupt signal
-     MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
-   }
+    // Write to End of interrupt signal
+    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
+  }
 
   // Ensure all GIC interrupts are Non-Secure
-   MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff);     // IRQs  0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
-   MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
-   MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
+  MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff);     // IRQs  0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
+  MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
+  MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
 
   // Ensure all interrupts can get through the priority mask
-   MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);
+  MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);
 }
 
 VOID
@@ -63,12 +63,12 @@ PL390GicEnableInterruptInterface (
      * Enable CPU inteface in Non-secure World
    * Signal Secure Interrupts to CPU using FIQ line *
    */
-    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
-        GIC_ICCICR_ENABLE_SECURE(1) |
-        GIC_ICCICR_ENABLE_NS(1) |
-        GIC_ICCICR_ACK_CTL(0) |
-        GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
-        GIC_ICCICR_USE_SBPR(0));
+  MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
+      GIC_ICCICR_ENABLE_SECURE(1) |
+      GIC_ICCICR_ENABLE_NS(1) |
+      GIC_ICCICR_ACK_CTL(0) |
+      GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
+      GIC_ICCICR_USE_SBPR(0));
 }
 
 VOID
@@ -77,7 +77,7 @@ PL390GicEnableDistributor (
   IN  INTN          GicDistributorBase
   )
 {
-    MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1);               // turn on the GIC distributor
+  MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1);               // turn on the GIC distributor
 }
 
 VOID
@@ -98,18 +98,18 @@ PL390GicAcknowledgeSgiFrom (
   IN  INTN          CoreId
   )
 {
-    INTN            InterruptId;
+  INTN            InterruptId;
 
-    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
+  InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
 
-    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
+  // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
   if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
-      //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
+    // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
     MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
-        return 1;
-    } else {
-        return 0;
-    }
+    return 1;
+  } else {
+    return 0;
+  }
 }
 
 UINT32
@@ -120,16 +120,16 @@ PL390GicAcknowledgeSgi2From (
   IN  INTN          SgiId
   )
 {
-    INTN            InterruptId;
+  INTN            InterruptId;
 
-    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
+  InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
 
-    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
+  // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
   if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
-      //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
+    // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
     MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
-        return 1;
-    } else {
-        return 0;
-    }
+    return 1;
+  } else {
+    return 0;
+  }
 }