X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPkg%2FInclude%2FLibrary%2FArmLib.h;h=58116663b28d8d9202af7c8a483cfae1b2d4a31b;hp=5663844b1f1890a6fdb91231f4cec7bb0cd2c732;hb=cf93a37859e6d06efdbc5b1a91a6bf66f06b578b;hpb=e359565ec271d7a3fc863293e9f1f607c938f0ce

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 5663844b1f..58116663b2 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -1,7 +1,7 @@
 /** @file
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -18,10 +18,12 @@
 
 #include <Uefi/UefiBaseType.h>
 
-#ifdef ARM_CPU_ARMv6
-#include <Chipset/ARM1176JZ-S.h>
+#ifdef MDE_CPU_ARM
+  #include <Chipset/ArmV7.h>
+#elif defined(MDE_CPU_AARCH64)
+  #include <Chipset/AArch64.h>
 #else
-#include <Chipset/ArmV7.h>
+ #error "Unknown chipset."
 #endif
 
 typedef enum {
@@ -70,7 +72,7 @@ typedef enum {
 typedef struct {
   EFI_PHYSICAL_ADDRESS          PhysicalBase;
   EFI_VIRTUAL_ADDRESS           VirtualBase;
-  UINTN                         Length;
+  UINT64                        Length;
   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
 } ARM_MEMORY_REGION_DESCRIPTOR;
 
@@ -112,14 +114,16 @@ typedef enum {
 //
 // ARM MP Core IDs
 //
-#define ARM_CORE_MASK         0xFF
-#define ARM_CLUSTER_MASK      (0xFF << 8)
+#define ARM_CORE_AFF0         0xFF
+#define ARM_CORE_AFF1         (0xFF << 8)
+#define ARM_CORE_AFF2         (0xFF << 16)
+#define ARM_CORE_AFF3         (0xFFULL << 32)
+
+#define ARM_CORE_MASK         ARM_CORE_AFF0
+#define ARM_CLUSTER_MASK      ARM_CORE_AFF1
 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
-// Get the position of the core for the Stack Offset (4 Core per Cluster)
-//   Position = (ClusterId * 4) + CoreId
-#define GET_CORE_POS(MpId)    ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))
 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 
 ARM_CACHE_TYPE
@@ -145,58 +149,70 @@ EFIAPI
 ArmDataCachePresent (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmDataCacheSize (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmDataCacheAssociativity (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmDataCacheLineLength (
   VOID
   );
-  
+
 BOOLEAN
 EFIAPI
 ArmInstructionCachePresent (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheSize (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheAssociativity (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheLineLength (
   VOID
   );
-  
-UINT32
+
+UINTN
 EFIAPI
-Cp15IdCode (
+ArmIsArchTimerImplemented (
   VOID
   );
-  
-UINT32
+
+UINTN
 EFIAPI
-Cp15CacheInfo (
+ArmReadIdPfr0 (
+  VOID
+  );
+
+UINTN
+EFIAPI
+ArmReadIdPfr1 (
+  VOID
+  );
+
+UINTN
+EFIAPI
+ArmCacheInfo (
   VOID
   );
 
@@ -255,6 +271,24 @@ ArmCleanInvalidateDataCacheEntryByMVA (
   IN  UINTN   Address
   );
 
+VOID
+EFIAPI
+ArmInvalidateDataCacheEntryBySetWay (
+  IN  UINTN  SetWayFormat
+  );
+
+VOID
+EFIAPI
+ArmCleanDataCacheEntryBySetWay (
+  IN  UINTN  SetWayFormat
+  );
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCacheEntryBySetWay (
+  IN  UINTN   SetWayFormat
+  );
+
 VOID
 EFIAPI
 ArmEnableDataCache (
@@ -278,7 +312,7 @@ EFIAPI
 ArmDisableInstructionCache (
   VOID
   );
-  
+
 VOID
 EFIAPI
 ArmEnableMmu (
@@ -293,13 +327,13 @@ ArmDisableMmu (
 
 VOID
 EFIAPI
-ArmDisableCachesAndMmu (
+ArmEnableCachesAndMmu (
   VOID
   );
 
 VOID
 EFIAPI
-ArmInvalidateInstructionAndDataTlb (
+ArmDisableCachesAndMmu (
   VOID
   );
 
@@ -321,9 +355,15 @@ ArmGetInterruptState (
   VOID
   );
 
+VOID
+EFIAPI
+ArmEnableAsynchronousAbort (
+  VOID
+  );
+
 UINTN
 EFIAPI
-ArmDisableIrq (
+ArmDisableAsynchronousAbort (
   VOID
   );
 
@@ -333,6 +373,12 @@ ArmEnableIrq (
   VOID
   );
 
+UINTN
+EFIAPI
+ArmDisableIrq (
+  VOID
+  );
+
 VOID
 EFIAPI
 ArmEnableFiq (
@@ -344,26 +390,29 @@ EFIAPI
 ArmDisableFiq (
   VOID
   );
-  
+
 BOOLEAN
 EFIAPI
 ArmGetFiqState (
   VOID
   );
 
+/**
+ * Invalidate Data and Instruction TLBs
+ */
 VOID
 EFIAPI
 ArmInvalidateTlb (
   VOID
   );
-  
+
 VOID
 EFIAPI
 ArmUpdateTranslationTableEntry (
   IN  VOID     *TranslationTableEntry,
   IN  VOID     *Mva
   );
-  
+
 VOID
 EFIAPI
 ArmSetDomainAccessControl (
@@ -382,32 +431,20 @@ ArmGetTTBR0BaseAddress (
   VOID
   );
 
-VOID
+RETURN_STATUS
 EFIAPI
 ArmConfigureMmu (
   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
-  OUT VOID                          **TranslationTableBase OPTIONAL,
+  OUT VOID                         **TranslationTableBase OPTIONAL,
   OUT UINTN                         *TranslationTableSize  OPTIONAL
   );
-  
+
 BOOLEAN
 EFIAPI
 ArmMmuEnabled (
   VOID
   );
-  
-VOID
-EFIAPI
-ArmSwitchProcessorMode (
-  IN ARM_PROCESSOR_MODE Mode
-  );
 
-ARM_PROCESSOR_MODE
-EFIAPI
-ArmProcessorMode (
-  VOID
-  );
-  
 VOID
 EFIAPI
 ArmEnableBranchPrediction (
@@ -432,18 +469,24 @@ ArmSetHighVectors (
   VOID
   );
 
+VOID
+EFIAPI
+ArmDrainWriteBuffer (
+  VOID
+  );
+
 VOID
 EFIAPI
 ArmDataMemoryBarrier (
   VOID
   );
-  
+
 VOID
 EFIAPI
-ArmDataSyncronizationBarrier (
+ArmDataSynchronizationBarrier (
   VOID
   );
-  
+
 VOID
 EFIAPI
 ArmInstructionSynchronizationBarrier (
@@ -453,10 +496,10 @@ ArmInstructionSynchronizationBarrier (
 VOID
 EFIAPI
 ArmWriteVBar (
-  IN  UINT32   VectorBase
+  IN  UINTN   VectorBase
   );
 
-UINT32
+UINTN
 EFIAPI
 ArmReadVBar (
   VOID
@@ -501,6 +544,7 @@ ArmCallWFE (
 VOID
 EFIAPI
 ArmCallWFI (
+
   VOID
   );
 
@@ -510,6 +554,12 @@ ArmReadMpidr (
   VOID
   );
 
+UINTN
+EFIAPI
+ArmReadMidr (
+  VOID
+  );
+
 UINT32
 EFIAPI
 ArmReadCpacr (
@@ -528,28 +578,28 @@ ArmEnableVFP (
   VOID
   );
 
-UINT32
-EFIAPI
-ArmReadNsacr (
-  VOID
-  );
+/**
+  Get the Secure Configuration Register value
 
-VOID
-EFIAPI
-ArmWriteNsacr (
-  IN  UINT32   SetWayFormat
-  );
+  @return   Value read from the Secure Configuration Register
 
+**/
 UINT32
 EFIAPI
 ArmReadScr (
   VOID
   );
 
+/**
+  Set the Secure Configuration Register
+
+  @param Value   Value to write to the Secure Configuration Register
+
+**/
 VOID
 EFIAPI
 ArmWriteScr (
-  IN  UINT32   SetWayFormat
+  IN  UINT32   Value
   );
 
 UINT32
@@ -582,4 +632,57 @@ ArmWriteHVBar (
   IN  UINTN   HypModeVectorBase
   );
 
+
+//
+// Helper functions for accessing CPU ACTLR
+//
+
+UINTN
+EFIAPI
+ArmReadCpuActlr (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmWriteCpuActlr (
+  IN  UINTN Val
+  );
+
+VOID
+EFIAPI
+ArmSetCpuActlrBit (
+  IN  UINTN    Bits
+  );
+
+VOID
+EFIAPI
+ArmUnsetCpuActlrBit (
+  IN  UINTN    Bits
+  );
+
+RETURN_STATUS
+ArmSetMemoryRegionNoExec (
+  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
+  IN  UINT64                    Length
+  );
+
+RETURN_STATUS
+ArmClearMemoryRegionNoExec (
+  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
+  IN  UINT64                    Length
+  );
+
+RETURN_STATUS
+ArmSetMemoryRegionReadOnly (
+  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
+  IN  UINT64                    Length
+  );
+
+RETURN_STATUS
+ArmClearMemoryRegionReadOnly (
+  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
+  IN  UINT64                    Length
+  );
+
 #endif // __ARM_LIB__