X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPkg%2FInclude%2FLibrary%2FArmLib.h;h=6566deebdde20861c8d93fd401cd14fe4f93a269;hp=1726984f5baf142672fb7b73904293f62f8dbf0f;hb=HEAD;hpb=9401d6f4b989d977f8b0aa4946168a92b748aead
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 1726984f5b..fa605f128b 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -1,58 +1,29 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
+ Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-#ifndef __ARM_LIB__
-#define __ARM_LIB__
+#ifndef ARM_LIB_H_
+#define ARM_LIB_H_
#include
#ifdef MDE_CPU_ARM
- #ifdef ARM_CPU_ARMv6
- #include
- #else
- #include
- #endif
-#elif defined(MDE_CPU_AARCH64)
+ #include
+#elif defined (MDE_CPU_AARCH64)
#include
#else
- #error "Unknown chipset."
+ #error "Unknown chipset."
#endif
-typedef enum {
- ARM_CACHE_TYPE_WRITE_BACK,
- ARM_CACHE_TYPE_UNKNOWN
-} ARM_CACHE_TYPE;
-
-typedef enum {
- ARM_CACHE_ARCHITECTURE_UNIFIED,
- ARM_CACHE_ARCHITECTURE_SEPARATE,
- ARM_CACHE_ARCHITECTURE_UNKNOWN
-} ARM_CACHE_ARCHITECTURE;
-
-typedef struct {
- ARM_CACHE_TYPE Type;
- ARM_CACHE_ARCHITECTURE Architecture;
- BOOLEAN DataCachePresent;
- UINTN DataCacheSize;
- UINTN DataCacheAssociativity;
- UINTN DataCacheLineLength;
- BOOLEAN InstructionCachePresent;
- UINTN InstructionCacheSize;
- UINTN InstructionCacheAssociativity;
- UINTN InstructionCacheLineLength;
-} ARM_CACHE_INFO;
+#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
+ EFI_MEMORY_WT | EFI_MEMORY_WB | \
+ EFI_MEMORY_UCE)
/**
* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
@@ -65,23 +36,35 @@ typedef enum {
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
+
+ // On some platforms, memory mapped flash region is designed as not supporting
+ // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
+ // need.
+ // Do NOT use below two attributes if you are not sure.
+ ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
+
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
} ARM_MEMORY_REGION_ATTRIBUTES;
-#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
+#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
typedef struct {
- EFI_PHYSICAL_ADDRESS PhysicalBase;
- EFI_VIRTUAL_ADDRESS VirtualBase;
- UINT64 Length;
- ARM_MEMORY_REGION_ATTRIBUTES Attributes;
+ EFI_PHYSICAL_ADDRESS PhysicalBase;
+ EFI_VIRTUAL_ADDRESS VirtualBase;
+ UINT64 Length;
+ ARM_MEMORY_REGION_ATTRIBUTES Attributes;
} ARM_MEMORY_REGION_DESCRIPTOR;
-typedef VOID (*CACHE_OPERATION)(VOID);
-typedef VOID (*LINE_OPERATION)(UINTN);
+typedef VOID (*CACHE_OPERATION)(
+ VOID
+ );
+typedef VOID (*LINE_OPERATION)(
+ UINTN
+ );
//
// ARM Processor Mode
@@ -101,93 +84,79 @@ typedef enum {
//
// ARM Cpu IDs
//
-#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
-#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
-#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
-#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
-#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
-#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
-
-#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
+#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
+#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
+#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
+#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
+#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
+#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
+
+#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
//
// ARM MP Core IDs
//
-#define ARM_CORE_MASK 0xFF
-#define ARM_CLUSTER_MASK (0xFF << 8)
-#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
-#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
-#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
-// Get the position of the core for the Stack Offset (4 Core per Cluster)
-// Position = (ClusterId * 4) + CoreId
-#define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))
-#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
-
-ARM_CACHE_TYPE
-EFIAPI
-ArmCacheType (
- VOID
+#define ARM_CORE_AFF0 0xFF
+#define ARM_CORE_AFF1 (0xFF << 8)
+#define ARM_CORE_AFF2 (0xFF << 16)
+#define ARM_CORE_AFF3 (0xFFULL << 32)
+
+#define ARM_CORE_MASK ARM_CORE_AFF0
+#define ARM_CLUSTER_MASK ARM_CORE_AFF1
+#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
+#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
+#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
+#define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)
+#define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)
+#define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)
+#define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)
+#define GET_MPIDR_AFFINITY_BITS(MpId) ((MpId) & 0xFF00FFFFFF)
+#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
+#define MPIDR_MT_BIT BIT24
+
+/** Reads the CCSIDR register for the specified cache.
+
+ @param CSSELR The CSSELR cache selection register value.
+
+ @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
+ Returns the contents of the CCSIDR register in AARCH32 mode.
+**/
+UINTN
+ReadCCSIDR (
+ IN UINT32 CSSELR
);
-ARM_CACHE_ARCHITECTURE
-EFIAPI
-ArmCacheArchitecture (
- VOID
- );
+/** Reads the CCSIDR2 for the specified cache.
-VOID
-EFIAPI
-ArmCacheInformation (
- OUT ARM_CACHE_INFO *CacheInfo
- );
+ @param CSSELR The CSSELR cache selection register value
-BOOLEAN
-EFIAPI
-ArmDataCachePresent (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmDataCacheSize (
- VOID
+ @return The contents of the CCSIDR2 register for the specified cache.
+**/
+UINT32
+ReadCCSIDR2 (
+ IN UINT32 CSSELR
);
-
-UINTN
-EFIAPI
-ArmDataCacheAssociativity (
+
+/** Reads the Cache Level ID (CLIDR) register.
+
+ @return The contents of the CLIDR_EL1 register.
+**/
+UINT32
+ReadCLIDR (
VOID
);
-
+
UINTN
EFIAPI
ArmDataCacheLineLength (
VOID
);
-
-BOOLEAN
-EFIAPI
-ArmInstructionCachePresent (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmInstructionCacheSize (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmInstructionCacheAssociativity (
- VOID
- );
-
+
UINTN
EFIAPI
ArmInstructionCacheLineLength (
@@ -196,31 +165,19 @@ ArmInstructionCacheLineLength (
UINTN
EFIAPI
-ArmIsArchTimerImplemented (
+ArmCacheWritebackGranule (
VOID
);
UINTN
EFIAPI
-ArmReadIdPfr0 (
+ArmIsArchTimerImplemented (
VOID
);
UINTN
EFIAPI
-ArmReadIdPfr1 (
- VOID
- );
-
-UINT32
-EFIAPI
-Cp15IdCode (
- VOID
- );
-
-UINT32
-EFIAPI
-Cp15CacheInfo (
+ArmCacheInfo (
VOID
);
@@ -236,7 +193,6 @@ ArmInvalidateDataCache (
VOID
);
-
VOID
EFIAPI
ArmCleanInvalidateDataCache (
@@ -251,32 +207,38 @@ ArmCleanDataCache (
VOID
EFIAPI
-ArmCleanDataCacheToPoU (
+ArmInvalidateInstructionCache (
VOID
);
VOID
EFIAPI
-ArmInvalidateInstructionCache (
- VOID
+ArmInvalidateDataCacheEntryByMVA (
+ IN UINTN Address
);
VOID
EFIAPI
-ArmInvalidateDataCacheEntryByMVA (
- IN UINTN Address
+ArmCleanDataCacheEntryToPoUByMVA (
+ IN UINTN Address
+ );
+
+VOID
+EFIAPI
+ArmInvalidateInstructionCacheEntryToPoUByMVA (
+ IN UINTN Address
);
VOID
EFIAPI
ArmCleanDataCacheEntryByMVA (
- IN UINTN Address
+ IN UINTN Address
);
VOID
EFIAPI
ArmCleanInvalidateDataCacheEntryByMVA (
- IN UINTN Address
+ IN UINTN Address
);
VOID
@@ -302,7 +264,7 @@ EFIAPI
ArmDisableInstructionCache (
VOID
);
-
+
VOID
EFIAPI
ArmEnableMmu (
@@ -317,13 +279,13 @@ ArmDisableMmu (
VOID
EFIAPI
-ArmDisableCachesAndMmu (
+ArmEnableCachesAndMmu (
VOID
);
VOID
EFIAPI
-ArmInvalidateInstructionAndDataTlb (
+ArmDisableCachesAndMmu (
VOID
);
@@ -345,9 +307,15 @@ ArmGetInterruptState (
VOID
);
+VOID
+EFIAPI
+ArmEnableAsynchronousAbort (
+ VOID
+ );
+
UINTN
EFIAPI
-ArmDisableIrq (
+ArmDisableAsynchronousAbort (
VOID
);
@@ -357,6 +325,12 @@ ArmEnableIrq (
VOID
);
+UINTN
+EFIAPI
+ArmDisableIrq (
+ VOID
+ );
+
VOID
EFIAPI
ArmEnableFiq (
@@ -368,26 +342,29 @@ EFIAPI
ArmDisableFiq (
VOID
);
-
+
BOOLEAN
EFIAPI
ArmGetFiqState (
VOID
);
+/**
+ * Invalidate Data and Instruction TLBs
+ */
VOID
EFIAPI
ArmInvalidateTlb (
VOID
);
-
+
VOID
EFIAPI
ArmUpdateTranslationTableEntry (
- IN VOID *TranslationTableEntry,
- IN VOID *Mva
+ IN VOID *TranslationTableEntry,
+ IN VOID *Mva
);
-
+
VOID
EFIAPI
ArmSetDomainAccessControl (
@@ -400,38 +377,24 @@ ArmSetTTBR0 (
IN VOID *TranslationTableBase
);
+VOID
+EFIAPI
+ArmSetTTBCR (
+ IN UINT32 Bits
+ );
+
VOID *
EFIAPI
ArmGetTTBR0BaseAddress (
VOID
);
-RETURN_STATUS
-EFIAPI
-ArmConfigureMmu (
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
- OUT VOID **TranslationTableBase OPTIONAL,
- OUT UINTN *TranslationTableSize OPTIONAL
- );
-
BOOLEAN
EFIAPI
ArmMmuEnabled (
VOID
);
-
-VOID
-EFIAPI
-ArmSwitchProcessorMode (
- IN ARM_PROCESSOR_MODE Mode
- );
-ARM_PROCESSOR_MODE
-EFIAPI
-ArmProcessorMode (
- VOID
- );
-
VOID
EFIAPI
ArmEnableBranchPrediction (
@@ -461,13 +424,13 @@ EFIAPI
ArmDataMemoryBarrier (
VOID
);
-
+
VOID
EFIAPI
-ArmDataSyncronizationBarrier (
+ArmDataSynchronizationBarrier (
VOID
);
-
+
VOID
EFIAPI
ArmInstructionSynchronizationBarrier (
@@ -477,7 +440,7 @@ ArmInstructionSynchronizationBarrier (
VOID
EFIAPI
ArmWriteVBar (
- IN UINTN VectorBase
+ IN UINTN VectorBase
);
UINTN
@@ -489,7 +452,7 @@ ArmReadVBar (
VOID
EFIAPI
ArmWriteAuxCr (
- IN UINT32 Bit
+ IN UINT32 Bit
);
UINT32
@@ -501,13 +464,13 @@ ArmReadAuxCr (
VOID
EFIAPI
ArmSetAuxCrBit (
- IN UINT32 Bits
+ IN UINT32 Bits
);
VOID
EFIAPI
ArmUnsetAuxCrBit (
- IN UINT32 Bits
+ IN UINT32 Bits
);
VOID
@@ -550,7 +513,7 @@ ArmReadCpacr (
VOID
EFIAPI
ArmWriteCpacr (
- IN UINT32 Access
+ IN UINT32 Access
);
VOID
@@ -559,16 +522,28 @@ ArmEnableVFP (
VOID
);
+/**
+ Get the Secure Configuration Register value
+
+ @return Value read from the Secure Configuration Register
+
+**/
UINT32
EFIAPI
ArmReadScr (
VOID
);
+/**
+ Set the Secure Configuration Register
+
+ @param Value Value to write to the Secure Configuration Register
+
+**/
VOID
EFIAPI
ArmWriteScr (
- IN UINT32 SetWayFormat
+ IN UINT32 Value
);
UINT32
@@ -580,7 +555,7 @@ ArmReadMVBar (
VOID
EFIAPI
ArmWriteMVBar (
- IN UINT32 VectorMonitorBase
+ IN UINT32 VectorMonitorBase
);
UINT32
@@ -589,6 +564,12 @@ ArmReadSctlr (
VOID
);
+VOID
+EFIAPI
+ArmWriteSctlr (
+ IN UINT32 Value
+ );
+
UINTN
EFIAPI
ArmReadHVBar (
@@ -598,7 +579,215 @@ ArmReadHVBar (
VOID
EFIAPI
ArmWriteHVBar (
- IN UINTN HypModeVectorBase
+ IN UINTN HypModeVectorBase
+ );
+
+//
+// Helper functions for accessing CPU ACTLR
+//
+
+UINTN
+EFIAPI
+ArmReadCpuActlr (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCpuActlr (
+ IN UINTN Val
+ );
+
+VOID
+EFIAPI
+ArmSetCpuActlrBit (
+ IN UINTN Bits
+ );
+
+VOID
+EFIAPI
+ArmUnsetCpuActlrBit (
+ IN UINTN Bits
+ );
+
+//
+// Accessors for the architected generic timer registers
+//
+
+#define ARM_ARCH_TIMER_ENABLE (1 << 0)
+#define ARM_ARCH_TIMER_IMASK (1 << 1)
+#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
+
+UINTN
+EFIAPI
+ArmReadCntFrq (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntFrq (
+ UINTN FreqInHz
+ );
+
+UINT64
+EFIAPI
+ArmReadCntPct (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmReadCntkCtl (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntkCtl (
+ UINTN Val
);
-#endif // __ARM_LIB__
+UINTN
+EFIAPI
+ArmReadCntpTval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntpTval (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntpCtl (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntpCtl (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntvTval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvTval (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntvCtl (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvCtl (
+ UINTN Val
+ );
+
+UINT64
+EFIAPI
+ArmReadCntvCt (
+ VOID
+ );
+
+UINT64
+EFIAPI
+ArmReadCntpCval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntpCval (
+ UINT64 Val
+ );
+
+UINT64
+EFIAPI
+ArmReadCntvCval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvCval (
+ UINT64 Val
+ );
+
+UINT64
+EFIAPI
+ArmReadCntvOff (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvOff (
+ UINT64 Val
+ );
+
+UINTN
+EFIAPI
+ArmGetPhysicalAddressBits (
+ VOID
+ );
+
+///
+/// ID Register Helper functions
+///
+
+/**
+ Check whether the CPU supports the GIC system register interface (any version)
+
+ @return Whether GIC System Register Interface is supported
+
+**/
+BOOLEAN
+EFIAPI
+ArmHasGicSystemRegisters (
+ VOID
+ );
+
+/** Checks if CCIDX is implemented.
+
+ @retval TRUE CCIDX is implemented.
+ @retval FALSE CCIDX is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasCcidx (
+ VOID
+ );
+
+#ifdef MDE_CPU_ARM
+///
+/// AArch32-only ID Register Helper functions
+///
+
+/**
+ Check whether the CPU supports the Security extensions
+
+ @return Whether the Security extensions are implemented
+
+**/
+BOOLEAN
+EFIAPI
+ArmHasSecurityExtensions (
+ VOID
+ );
+
+#endif // MDE_CPU_ARM
+
+#endif // ARM_LIB_H_