X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPkg%2FInclude%2FLibrary%2FArmLib.h;h=9a804c15fdb6f168528d7383db7688fccc01dc7d;hp=4550ea6ba0a3763e07d92656e1b920d7b16b7de8;hb=95d04ebca8be8f71a23e85a2f4822ba90a2e32cc;hpb=47585ed568ebcda8718928c254b9669fd6ee923e
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 4550ea6ba0..9a804c15fd 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.
+ Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -18,35 +18,17 @@
#include
-#ifdef ARM_CPU_ARMv6
-#include
+#ifdef MDE_CPU_ARM
+ #include
+#elif defined(MDE_CPU_AARCH64)
+ #include
#else
-#include
+ #error "Unknown chipset."
#endif
-typedef enum {
- ARM_CACHE_TYPE_WRITE_BACK,
- ARM_CACHE_TYPE_UNKNOWN
-} ARM_CACHE_TYPE;
-
-typedef enum {
- ARM_CACHE_ARCHITECTURE_UNIFIED,
- ARM_CACHE_ARCHITECTURE_SEPARATE,
- ARM_CACHE_ARCHITECTURE_UNKNOWN
-} ARM_CACHE_ARCHITECTURE;
-
-typedef struct {
- ARM_CACHE_TYPE Type;
- ARM_CACHE_ARCHITECTURE Architecture;
- BOOLEAN DataCachePresent;
- UINTN DataCacheSize;
- UINTN DataCacheAssociativity;
- UINTN DataCacheLineLength;
- BOOLEAN InstructionCachePresent;
- UINTN InstructionCacheSize;
- UINTN InstructionCacheAssociativity;
- UINTN InstructionCacheLineLength;
-} ARM_CACHE_INFO;
+#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
+ EFI_MEMORY_WT | EFI_MEMORY_WB | \
+ EFI_MEMORY_UCE)
/**
* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
@@ -59,6 +41,14 @@ typedef enum {
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
+
+ // On some platforms, memory mapped flash region is designed as not supporting
+ // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
+ // need.
+ // Do NOT use below two attributes if you are not sure.
+ ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
+
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
@@ -70,7 +60,7 @@ typedef enum {
typedef struct {
EFI_PHYSICAL_ADDRESS PhysicalBase;
EFI_VIRTUAL_ADDRESS VirtualBase;
- UINTN Length;
+ UINT64 Length;
ARM_MEMORY_REGION_ATTRIBUTES Attributes;
} ARM_MEMORY_REGION_DESCRIPTOR;
@@ -112,91 +102,57 @@ typedef enum {
//
// ARM MP Core IDs
//
-#define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
-#define ARM_CORE_MASK 0xFF
-#define ARM_CLUSTER_MASK (0xFF << 8)
+#define ARM_CORE_AFF0 0xFF
+#define ARM_CORE_AFF1 (0xFF << 8)
+#define ARM_CORE_AFF2 (0xFF << 16)
+#define ARM_CORE_AFF3 (0xFFULL << 32)
+
+#define ARM_CORE_MASK ARM_CORE_AFF0
+#define ARM_CLUSTER_MASK ARM_CORE_AFF1
#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
-// Get the position of the core for the Stack Offset (4 Core per Cluster)
-// Position = (ClusterId * 4) + CoreId
-#define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))
+#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
-ARM_CACHE_TYPE
-EFIAPI
-ArmCacheType (
- VOID
- );
-
-ARM_CACHE_ARCHITECTURE
+UINTN
EFIAPI
-ArmCacheArchitecture (
+ArmDataCacheLineLength (
VOID
);
-VOID
-EFIAPI
-ArmCacheInformation (
- OUT ARM_CACHE_INFO *CacheInfo
- );
-
-BOOLEAN
-EFIAPI
-ArmDataCachePresent (
- VOID
- );
-
UINTN
EFIAPI
-ArmDataCacheSize (
+ArmInstructionCacheLineLength (
VOID
);
-
+
UINTN
EFIAPI
-ArmDataCacheAssociativity (
+ArmCacheWritebackGranule (
VOID
);
-
+
UINTN
EFIAPI
-ArmDataCacheLineLength (
- VOID
- );
-
-BOOLEAN
-EFIAPI
-ArmInstructionCachePresent (
+ArmIsArchTimerImplemented (
VOID
);
-
+
UINTN
EFIAPI
-ArmInstructionCacheSize (
+ArmReadIdPfr0 (
VOID
);
-
+
UINTN
EFIAPI
-ArmInstructionCacheAssociativity (
+ArmReadIdPfr1 (
VOID
);
-
+
UINTN
EFIAPI
-ArmInstructionCacheLineLength (
- VOID
- );
-
-UINT32
-EFIAPI
-Cp15IdCode (
- VOID
- );
-
-UINT32
-EFIAPI
-Cp15CacheInfo (
+ArmCacheInfo (
VOID
);
@@ -227,34 +183,58 @@ ArmCleanDataCache (
VOID
EFIAPI
-ArmCleanDataCacheToPoU (
+ArmInvalidateInstructionCache (
VOID
);
VOID
EFIAPI
-ArmInvalidateInstructionCache (
- VOID
+ArmInvalidateDataCacheEntryByMVA (
+ IN UINTN Address
);
VOID
EFIAPI
-ArmInvalidateDataCacheEntryByMVA (
+ArmCleanDataCacheEntryToPoUByMVA (
IN UINTN Address
);
VOID
EFIAPI
-ArmCleanDataCacheEntryByMVA (
+ArmInvalidateInstructionCacheEntryToPoUByMVA (
IN UINTN Address
);
+VOID
+EFIAPI
+ArmCleanDataCacheEntryByMVA (
+IN UINTN Address
+);
+
VOID
EFIAPI
ArmCleanInvalidateDataCacheEntryByMVA (
IN UINTN Address
);
+VOID
+EFIAPI
+ArmInvalidateDataCacheEntryBySetWay (
+ IN UINTN SetWayFormat
+ );
+
+VOID
+EFIAPI
+ArmCleanDataCacheEntryBySetWay (
+ IN UINTN SetWayFormat
+ );
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCacheEntryBySetWay (
+ IN UINTN SetWayFormat
+ );
+
VOID
EFIAPI
ArmEnableDataCache (
@@ -278,7 +258,7 @@ EFIAPI
ArmDisableInstructionCache (
VOID
);
-
+
VOID
EFIAPI
ArmEnableMmu (
@@ -293,13 +273,13 @@ ArmDisableMmu (
VOID
EFIAPI
-ArmDisableCachesAndMmu (
+ArmEnableCachesAndMmu (
VOID
);
VOID
EFIAPI
-ArmInvalidateInstructionAndDataTlb (
+ArmDisableCachesAndMmu (
VOID
);
@@ -321,9 +301,15 @@ ArmGetInterruptState (
VOID
);
+VOID
+EFIAPI
+ArmEnableAsynchronousAbort (
+ VOID
+ );
+
UINTN
EFIAPI
-ArmDisableIrq (
+ArmDisableAsynchronousAbort (
VOID
);
@@ -333,6 +319,12 @@ ArmEnableIrq (
VOID
);
+UINTN
+EFIAPI
+ArmDisableIrq (
+ VOID
+ );
+
VOID
EFIAPI
ArmEnableFiq (
@@ -344,26 +336,29 @@ EFIAPI
ArmDisableFiq (
VOID
);
-
+
BOOLEAN
EFIAPI
ArmGetFiqState (
VOID
);
+/**
+ * Invalidate Data and Instruction TLBs
+ */
VOID
EFIAPI
ArmInvalidateTlb (
VOID
);
-
+
VOID
EFIAPI
ArmUpdateTranslationTableEntry (
IN VOID *TranslationTableEntry,
IN VOID *Mva
);
-
+
VOID
EFIAPI
ArmSetDomainAccessControl (
@@ -376,38 +371,24 @@ ArmSetTTBR0 (
IN VOID *TranslationTableBase
);
+VOID
+EFIAPI
+ArmSetTTBCR (
+ IN UINT32 Bits
+ );
+
VOID *
EFIAPI
ArmGetTTBR0BaseAddress (
VOID
);
-VOID
-EFIAPI
-ArmConfigureMmu (
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
- OUT VOID **TranslationTableBase OPTIONAL,
- OUT UINTN *TranslationTableSize OPTIONAL
- );
-
BOOLEAN
EFIAPI
ArmMmuEnabled (
VOID
);
-
-VOID
-EFIAPI
-ArmSwitchProcessorMode (
- IN ARM_PROCESSOR_MODE Mode
- );
-ARM_PROCESSOR_MODE
-EFIAPI
-ArmProcessorMode (
- VOID
- );
-
VOID
EFIAPI
ArmEnableBranchPrediction (
@@ -437,13 +418,13 @@ EFIAPI
ArmDataMemoryBarrier (
VOID
);
-
+
VOID
EFIAPI
-ArmDataSyncronizationBarrier (
+ArmDataSynchronizationBarrier (
VOID
);
-
+
VOID
EFIAPI
ArmInstructionSynchronizationBarrier (
@@ -453,10 +434,10 @@ ArmInstructionSynchronizationBarrier (
VOID
EFIAPI
ArmWriteVBar (
- IN UINT32 VectorBase
+ IN UINTN VectorBase
);
-UINT32
+UINTN
EFIAPI
ArmReadVBar (
VOID
@@ -501,6 +482,7 @@ ArmCallWFE (
VOID
EFIAPI
ArmCallWFI (
+
VOID
);
@@ -510,6 +492,12 @@ ArmReadMpidr (
VOID
);
+UINTN
+EFIAPI
+ArmReadMidr (
+ VOID
+ );
+
UINT32
EFIAPI
ArmReadCpacr (
@@ -528,28 +516,28 @@ ArmEnableVFP (
VOID
);
-UINT32
-EFIAPI
-ArmReadNsacr (
- VOID
- );
+/**
+ Get the Secure Configuration Register value
-VOID
-EFIAPI
-ArmWriteNsacr (
- IN UINT32 SetWayFormat
- );
+ @return Value read from the Secure Configuration Register
+**/
UINT32
EFIAPI
ArmReadScr (
VOID
);
+/**
+ Set the Secure Configuration Register
+
+ @param Value Value to write to the Secure Configuration Register
+
+**/
VOID
EFIAPI
ArmWriteScr (
- IN UINT32 SetWayFormat
+ IN UINT32 Value
);
UINT32
@@ -570,4 +558,185 @@ ArmReadSctlr (
VOID
);
+VOID
+EFIAPI
+ArmWriteSctlr (
+ IN UINT32 Value
+ );
+
+UINTN
+EFIAPI
+ArmReadHVBar (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteHVBar (
+ IN UINTN HypModeVectorBase
+ );
+
+
+//
+// Helper functions for accessing CPU ACTLR
+//
+
+UINTN
+EFIAPI
+ArmReadCpuActlr (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCpuActlr (
+ IN UINTN Val
+ );
+
+VOID
+EFIAPI
+ArmSetCpuActlrBit (
+ IN UINTN Bits
+ );
+
+VOID
+EFIAPI
+ArmUnsetCpuActlrBit (
+ IN UINTN Bits
+ );
+
+//
+// Accessors for the architected generic timer registers
+//
+
+#define ARM_ARCH_TIMER_ENABLE (1 << 0)
+#define ARM_ARCH_TIMER_IMASK (1 << 1)
+#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
+
+UINTN
+EFIAPI
+ArmReadCntFrq (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntFrq (
+ UINTN FreqInHz
+ );
+
+UINT64
+EFIAPI
+ArmReadCntPct (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmReadCntkCtl (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntkCtl (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntpTval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntpTval (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntpCtl (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntpCtl (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntvTval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvTval (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntvCtl (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvCtl (
+ UINTN Val
+ );
+
+UINT64
+EFIAPI
+ArmReadCntvCt (
+ VOID
+ );
+
+UINT64
+EFIAPI
+ArmReadCntpCval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntpCval (
+ UINT64 Val
+ );
+
+UINT64
+EFIAPI
+ArmReadCntvCval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvCval (
+ UINT64 Val
+ );
+
+UINT64
+EFIAPI
+ArmReadCntvOff (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvOff (
+ UINT64 Val
+ );
+
+UINTN
+EFIAPI
+ArmGetPhysicalAddressBits (
+ VOID
+ );
+
#endif // __ARM_LIB__