X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPkg%2FInclude%2FLibrary%2FArmLib.h;h=9a804c15fdb6f168528d7383db7688fccc01dc7d;hp=7a0467130d5e8ee3de9005914a15551e95f4bd0f;hb=95d04ebca8be8f71a23e85a2f4822ba90a2e32cc;hpb=d9bd3f11cb47f8026a44721670f4abdfb9728a2a
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 7a0467130d..9a804c15fd 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -19,40 +19,16 @@
#include
#ifdef MDE_CPU_ARM
- #ifdef ARM_CPU_ARMv6
- #include
- #else
- #include
- #endif
+ #include
#elif defined(MDE_CPU_AARCH64)
#include
#else
#error "Unknown chipset."
#endif
-typedef enum {
- ARM_CACHE_TYPE_WRITE_BACK,
- ARM_CACHE_TYPE_UNKNOWN
-} ARM_CACHE_TYPE;
-
-typedef enum {
- ARM_CACHE_ARCHITECTURE_UNIFIED,
- ARM_CACHE_ARCHITECTURE_SEPARATE,
- ARM_CACHE_ARCHITECTURE_UNKNOWN
-} ARM_CACHE_ARCHITECTURE;
-
-typedef struct {
- ARM_CACHE_TYPE Type;
- ARM_CACHE_ARCHITECTURE Architecture;
- BOOLEAN DataCachePresent;
- UINTN DataCacheSize;
- UINTN DataCacheAssociativity;
- UINTN DataCacheLineLength;
- BOOLEAN InstructionCachePresent;
- UINTN InstructionCacheSize;
- UINTN InstructionCacheAssociativity;
- UINTN InstructionCacheLineLength;
-} ARM_CACHE_INFO;
+#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
+ EFI_MEMORY_WT | EFI_MEMORY_WB | \
+ EFI_MEMORY_UCE)
/**
* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
@@ -65,6 +41,14 @@ typedef enum {
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
+
+ // On some platforms, memory mapped flash region is designed as not supporting
+ // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
+ // need.
+ // Do NOT use below two attributes if you are not sure.
+ ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
+
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
@@ -118,79 +102,33 @@ typedef enum {
//
// ARM MP Core IDs
//
-#define ARM_CORE_MASK 0xFF
-#define ARM_CLUSTER_MASK (0xFF << 8)
+#define ARM_CORE_AFF0 0xFF
+#define ARM_CORE_AFF1 (0xFF << 8)
+#define ARM_CORE_AFF2 (0xFF << 16)
+#define ARM_CORE_AFF3 (0xFFULL << 32)
+
+#define ARM_CORE_MASK ARM_CORE_AFF0
+#define ARM_CLUSTER_MASK ARM_CORE_AFF1
#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
-// Get the position of the core for the Stack Offset (4 Core per Cluster)
-// Position = (ClusterId * 4) + CoreId
-#define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
-ARM_CACHE_TYPE
-EFIAPI
-ArmCacheType (
- VOID
- );
-
-ARM_CACHE_ARCHITECTURE
-EFIAPI
-ArmCacheArchitecture (
- VOID
- );
-
-VOID
-EFIAPI
-ArmCacheInformation (
- OUT ARM_CACHE_INFO *CacheInfo
- );
-
-BOOLEAN
-EFIAPI
-ArmDataCachePresent (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmDataCacheSize (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmDataCacheAssociativity (
- VOID
- );
-
UINTN
EFIAPI
ArmDataCacheLineLength (
VOID
);
-
-BOOLEAN
-EFIAPI
-ArmInstructionCachePresent (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmInstructionCacheSize (
- VOID
- );
-
+
UINTN
EFIAPI
-ArmInstructionCacheAssociativity (
+ArmInstructionCacheLineLength (
VOID
);
-
+
UINTN
EFIAPI
-ArmInstructionCacheLineLength (
+ArmCacheWritebackGranule (
VOID
);
@@ -212,9 +150,9 @@ ArmReadIdPfr1 (
VOID
);
-UINT32
+UINTN
EFIAPI
-Cp15CacheInfo (
+ArmCacheInfo (
VOID
);
@@ -245,28 +183,34 @@ ArmCleanDataCache (
VOID
EFIAPI
-ArmCleanDataCacheToPoU (
+ArmInvalidateInstructionCache (
VOID
);
VOID
EFIAPI
-ArmInvalidateInstructionCache (
- VOID
+ArmInvalidateDataCacheEntryByMVA (
+ IN UINTN Address
);
VOID
EFIAPI
-ArmInvalidateDataCacheEntryByMVA (
+ArmCleanDataCacheEntryToPoUByMVA (
IN UINTN Address
);
VOID
EFIAPI
-ArmCleanDataCacheEntryByMVA (
+ArmInvalidateInstructionCacheEntryToPoUByMVA (
IN UINTN Address
);
+VOID
+EFIAPI
+ArmCleanDataCacheEntryByMVA (
+IN UINTN Address
+);
+
VOID
EFIAPI
ArmCleanInvalidateDataCacheEntryByMVA (
@@ -314,7 +258,7 @@ EFIAPI
ArmDisableInstructionCache (
VOID
);
-
+
VOID
EFIAPI
ArmEnableMmu (
@@ -339,12 +283,6 @@ ArmDisableCachesAndMmu (
VOID
);
-VOID
-EFIAPI
-ArmInvalidateInstructionAndDataTlb (
- VOID
- );
-
VOID
EFIAPI
ArmEnableInterrupts (
@@ -398,26 +336,29 @@ EFIAPI
ArmDisableFiq (
VOID
);
-
+
BOOLEAN
EFIAPI
ArmGetFiqState (
VOID
);
+/**
+ * Invalidate Data and Instruction TLBs
+ */
VOID
EFIAPI
ArmInvalidateTlb (
VOID
);
-
+
VOID
EFIAPI
ArmUpdateTranslationTableEntry (
IN VOID *TranslationTableEntry,
IN VOID *Mva
);
-
+
VOID
EFIAPI
ArmSetDomainAccessControl (
@@ -430,26 +371,24 @@ ArmSetTTBR0 (
IN VOID *TranslationTableBase
);
+VOID
+EFIAPI
+ArmSetTTBCR (
+ IN UINT32 Bits
+ );
+
VOID *
EFIAPI
ArmGetTTBR0BaseAddress (
VOID
);
-RETURN_STATUS
-EFIAPI
-ArmConfigureMmu (
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
- OUT VOID **TranslationTableBase OPTIONAL,
- OUT UINTN *TranslationTableSize OPTIONAL
- );
-
BOOLEAN
EFIAPI
ArmMmuEnabled (
VOID
);
-
+
VOID
EFIAPI
ArmEnableBranchPrediction (
@@ -474,24 +413,18 @@ ArmSetHighVectors (
VOID
);
-VOID
-EFIAPI
-ArmDrainWriteBuffer (
- VOID
- );
-
VOID
EFIAPI
ArmDataMemoryBarrier (
VOID
);
-
+
VOID
EFIAPI
-ArmDataSyncronizationBarrier (
+ArmDataSynchronizationBarrier (
VOID
);
-
+
VOID
EFIAPI
ArmInstructionSynchronizationBarrier (
@@ -583,16 +516,28 @@ ArmEnableVFP (
VOID
);
+/**
+ Get the Secure Configuration Register value
+
+ @return Value read from the Secure Configuration Register
+
+**/
UINT32
EFIAPI
ArmReadScr (
VOID
);
+/**
+ Set the Secure Configuration Register
+
+ @param Value Value to write to the Secure Configuration Register
+
+**/
VOID
EFIAPI
ArmWriteScr (
- IN UINT32 SetWayFormat
+ IN UINT32 Value
);
UINT32
@@ -613,6 +558,12 @@ ArmReadSctlr (
VOID
);
+VOID
+EFIAPI
+ArmWriteSctlr (
+ IN UINT32 Value
+ );
+
UINTN
EFIAPI
ArmReadHVBar (
@@ -625,4 +576,167 @@ ArmWriteHVBar (
IN UINTN HypModeVectorBase
);
+
+//
+// Helper functions for accessing CPU ACTLR
+//
+
+UINTN
+EFIAPI
+ArmReadCpuActlr (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCpuActlr (
+ IN UINTN Val
+ );
+
+VOID
+EFIAPI
+ArmSetCpuActlrBit (
+ IN UINTN Bits
+ );
+
+VOID
+EFIAPI
+ArmUnsetCpuActlrBit (
+ IN UINTN Bits
+ );
+
+//
+// Accessors for the architected generic timer registers
+//
+
+#define ARM_ARCH_TIMER_ENABLE (1 << 0)
+#define ARM_ARCH_TIMER_IMASK (1 << 1)
+#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
+
+UINTN
+EFIAPI
+ArmReadCntFrq (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntFrq (
+ UINTN FreqInHz
+ );
+
+UINT64
+EFIAPI
+ArmReadCntPct (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmReadCntkCtl (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntkCtl (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntpTval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntpTval (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntpCtl (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntpCtl (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntvTval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvTval (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntvCtl (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvCtl (
+ UINTN Val
+ );
+
+UINT64
+EFIAPI
+ArmReadCntvCt (
+ VOID
+ );
+
+UINT64
+EFIAPI
+ArmReadCntpCval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntpCval (
+ UINT64 Val
+ );
+
+UINT64
+EFIAPI
+ArmReadCntvCval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvCval (
+ UINT64 Val
+ );
+
+UINT64
+EFIAPI
+ArmReadCntvOff (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvOff (
+ UINT64 Val
+ );
+
+UINTN
+EFIAPI
+ArmGetPhysicalAddressBits (
+ VOID
+ );
+
#endif // __ARM_LIB__