X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPkg%2FLibrary%2FArmLib%2FArmV7%2FArmLibSupport.asm;h=7099ced8f4dc04db3b077314b536ce2f25ae3281;hp=5d3083457ea698b7a2b35f5f48a01f157cbca702;hb=1bfda055dfbc52678655ab2ded721f9f7c0cd496;hpb=98bc0c8c056271095ae2a3a9ab7f2c3ccd64117e

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
index 5d3083457e..7099ced8f4 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
@@ -1,8 +1,8 @@
 //------------------------------------------------------------------------------ 
 //
-// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
 //
-// All rights reserved. This program and the accompanying materials
+// This program and the accompanying materials
 // are licensed and made available under the terms and conditions of the BSD License
 // which accompanies this distribution.  The full text of the license may be found at
 // http://opensource.org/licenses/bsd-license.php
@@ -15,19 +15,32 @@
 
     EXPORT  Cp15IdCode
     EXPORT  Cp15CacheInfo
+    EXPORT  ArmIsMPCore
+    EXPORT  ArmEnableAsynchronousAbort
+    EXPORT  ArmDisableAsynchronousAbort
+    EXPORT  ArmEnableIrq
+    EXPORT  ArmDisableIrq
+    EXPORT  ArmGetInterruptState
+    EXPORT  ArmEnableFiq
+    EXPORT  ArmDisableFiq
     EXPORT  ArmEnableInterrupts
     EXPORT  ArmDisableInterrupts
-    EXPORT  ArmGetInterruptState
+    EXPORT  ArmGetFiqState
     EXPORT  ArmInvalidateTlb
-    EXPORT  ArmSetTranslationTableBaseAddress
-    EXPORT  ArmGetTranslationTableBaseAddress
+    EXPORT  ArmSetTTBR0
+    EXPORT  ArmGetTTBR0BaseAddress
     EXPORT  ArmSetDomainAccessControl
+    EXPORT  ArmUpdateTranslationTableEntry
     EXPORT  CPSRMaskInsert
     EXPORT  CPSRRead
     EXPORT  ReadCCSIDR
-
+    EXPORT  ReadCLIDR
+    
     AREA ArmLibSupport, CODE, READONLY
 
+
+//------------------------------------------------------------------------------
+
 Cp15IdCode
   mrc     p15,0,R0,c0,c0,0
   bx      LR
@@ -36,17 +49,64 @@ Cp15CacheInfo
   mrc     p15,0,R0,c0,c0,1
   bx      LR
 
-ArmEnableInterrupts
-  CPSIE   i
+ArmIsMPCore
+  mrc     p15,0,R0,c0,c0,5
+  // Get Multiprocessing extension (bit31) & U bit (bit30)
+  and     R0, R0, #0xC0000000
+  // if bit30 == 0 then the processor is part of a multiprocessor system)
+  and     R0, R0, #0x80000000
+  bx      LR
+
+ArmEnableAsynchronousAbort
+  cpsie   a
+  isb
+  bx      LR
+
+ArmDisableAsynchronousAbort
+  cpsid   a
+  isb
+  bx      LR
+
+ArmEnableIrq
+  cpsie   i
+  isb
 	bx      LR
 
-ArmDisableInterrupts
-  CPSID   i
+ArmDisableIrq
+  cpsid   i
+  isb
+	bx      LR
+
+ArmEnableFiq
+  cpsie   f
+  isb
 	bx      LR
 
+ArmDisableFiq
+  cpsid   f
+  isb
+  bx      LR
+
+ArmEnableInterrupts
+  cpsie   if
+  isb
+  bx      LR
+
+ArmDisableInterrupts
+  cpsid   if
+  isb
+  bx      LR
+
 ArmGetInterruptState
+  mrs     R0,CPSR
+  tst     R0,#0x80	    ;Check if IRQ is enabled.
+  moveq   R0,#1
+  movne   R0,#0
+	bx      LR
+
+ArmGetFiqState
 	mrs     R0,CPSR
-	tst     R0,#0x80	    ;Check if IRQ is enabled.
+	tst     R0,#0x40	    ;Check if FIQ is enabled.
 	moveq   R0,#1
 	movne   R0,#0
 	bx      LR
@@ -54,22 +114,42 @@ ArmGetInterruptState
 ArmInvalidateTlb
   mov     r0,#0
   mcr     p15,0,r0,c8,c7,0
-  ISB
+  mcr     p15,0,R9,c7,c5,6      ; BPIALL Invalidate Branch predictor array. R9 == NoOp
+  dsb
+  isb
   bx      lr
 
-ArmSetTranslationTableBaseAddress
+ArmSetTTBR0
   mcr     p15,0,r0,c2,c0,0
-  ISB
+  isb
   bx      lr
 
-ArmGetTranslationTableBaseAddress
+ArmGetTTBR0BaseAddress
   mrc     p15,0,r0,c2,c0,0
-  ISB
+  ldr	  r1, = 0xFFFFC000
+  and     r0, r0, r1
+  isb
   bx      lr
 
+
 ArmSetDomainAccessControl
   mcr     p15,0,r0,c3,c0,0
-  ISB
+  isb
+  bx      lr
+
+//
+//VOID
+//ArmUpdateTranslationTableEntry (
+//  IN VOID  *TranslationTableEntry  // R0
+//  IN VOID  *MVA                    // R1
+//  );
+ArmUpdateTranslationTableEntry
+  mcr     p15,0,R0,c7,c14,1     ; DCCIMVAC Clean data cache by MVA
+  dsb
+  mcr     p15,0,R1,c8,c7,1      ; TLBIMVA TLB Invalidate MVA  
+  mcr     p15,0,R9,c7,c5,6      ; BPIALL Invalidate Branch predictor array. R9 == NoOp
+  dsb
+  isb
   bx      lr
 
 CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to insert
@@ -80,7 +160,7 @@ CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to in
   and     r1, r1, r0        ; clear bits outside the mask in the input
   orr     r2, r2, r1        ; set field
   msr     cpsr_cxsf, r2     ; write back cpsr (may have caused a mode switch)
-  ISB
+  isb
   mov     sp, r3            ; restore stack pointer
   ldmfd   sp!, {r4-r12, lr} ; restore registers
   bx      lr                ; return (hopefully thumb-safe!)
@@ -95,10 +175,10 @@ CPSRRead
 //   IN UINT32 CSSELR
 //   )  
 ReadCCSIDR
-  MCR p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
-  ISB
-  MRC p15,1,<Rt>,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
-  BX  lr
+  mcr p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
+  isb
+  mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
+  bx  lr
   
 
 // UINT32 
@@ -106,7 +186,7 @@ ReadCCSIDR
 //   IN UINT32 CSSELR
 //   )  
 ReadCLIDR
-  MRC p15,1,<Rt>,c0,c0,1 ; Read CP15 Cache Level ID Register
-  END
-
-
+  mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
+  bx  lr
+  
+END