X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPkg%2FLibrary%2FArmLib%2FArmV7%2FArmV7Mmu.c;h=7881a9b9fae2215473a95c94e5e8415f20ad787c;hp=f57e48b3a5ad32c42de0a73e4caad65dbecff2c6;hb=918c653e1f3fdcb46acadbb65a431391fcd388d2;hpb=bd6b97994ab6219c74033a7e68a503dbb8d56f9f

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
index f57e48b3a5..7881a9b9fa 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
@@ -1,7 +1,7 @@
 /** @file
 *  File managing the MMU for ARMv7 architecture
 *
-*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
 *  
 *  This program and the accompanying materials                          
 *  are licensed and made available under the terms and conditions of the BSD License         
@@ -41,19 +41,19 @@ PopulateLevel2PageTable (
 
   switch (Attributes) {
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
       PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
       break;
     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
       PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;
       break;
     case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE:
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
       PageAttributes = TT_DESCRIPTOR_PAGE_DEVICE;
       break;
     case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
       PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;
       break;
     default:
@@ -146,16 +146,16 @@ FillTranslationTable (
     case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
       break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
       break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
       Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
       break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE:
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
       Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);
       break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:
+    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
       break;
     default:
@@ -214,7 +214,7 @@ ArmConfigureMmu (
     *TranslationTableBase = (VOID *)TranslationTable;
   }
   
-  if (TranslationTableBase != NULL) {
+  if (TranslationTableSize != NULL) {
     *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;
   }
 
@@ -222,10 +222,10 @@ ArmConfigureMmu (
 
   ArmCleanInvalidateDataCache ();
   ArmInvalidateInstructionCache ();
-  ArmInvalidateTlb ();
 
   ArmDisableDataCache ();
   ArmDisableInstructionCache();
+  // TLBs are also invalidated when calling ArmDisableMmu()
   ArmDisableMmu ();
 
   // Make sure nothing sneaked into the cache
@@ -235,7 +235,7 @@ ArmConfigureMmu (
   TranslationTableAttribute = (ARM_MEMORY_REGION_ATTRIBUTES)0;
   while (MemoryTable->Length != 0) {
     // Find the memory attribute for the Translation Table
-    if ((TranslationTable >= MemoryTable->PhysicalBase) && (TranslationTable < MemoryTable->PhysicalBase + MemoryTable->Length)) {
+    if ((TranslationTable >= MemoryTable->PhysicalBase) && (TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {
       TranslationTableAttribute = MemoryTable->Attributes;
     }
 
@@ -245,20 +245,20 @@ ArmConfigureMmu (
 
   // Translate the Memory Attributes into Translation Table Register Attributes
   if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) || 
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED)) {
+      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
     TTBRAttributes = TTBR_NON_CACHEABLE;
   } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || 
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK)) {
+      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
     TTBRAttributes = TTBR_WRITE_BACK_ALLOC;
   } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) || 
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH)) {
+      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
     TTBRAttributes = TTBR_WRITE_THROUGH_NO_ALLOC;
   } else {
     //TODO: We should raise an error here
     TTBRAttributes = TTBR_NON_CACHEABLE;
   }
 
-  ArmSetTTBR0 ((VOID *)(UINTN)((TranslationTable & 0xFFFFC000) | (TTBRAttributes & 0x7F)));
+  ArmSetTTBR0 ((VOID *)(UINTN)((TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));
     
   ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
                              DOMAIN_ACCESS_CONTROL_NONE(14) |