X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPkg%2FLibrary%2FArmLib%2FArmV7%2FArmV7Support.asm;fp=ArmPkg%2FLibrary%2FArmLib%2FArmV7%2FArmV7Support.asm;h=368138933a356fdddec7ebc3951c11a685227eef;hp=4808c7ba748015fb00e77fe0838e7c182990bc27;hb=3402aac7d985bf8a9f9d3c639f3fe93609380513;hpb=62d441fb17d59958bf00c4a1f3b52bf6a0b40b24 diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index 4808c7ba74..368138933a 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -1,4 +1,4 @@ -//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ // // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. @@ -63,13 +63,13 @@ CTRL_I_BIT EQU (1 << 12) ArmInvalidateDataCacheEntryByMVA - mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line + mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line dsb isb bx lr ArmCleanDataCacheEntryByMVA - mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line + mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line dsb isb bx lr @@ -83,21 +83,21 @@ ArmCleanInvalidateDataCacheEntryByMVA ArmInvalidateDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line + mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line dsb isb bx lr ArmCleanInvalidateDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line + mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line dsb isb bx lr ArmCleanDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c10, 2 ; Clean this line + mcr p15, 0, r0, c7, c10, 2 ; Clean this line dsb isb bx lr @@ -150,7 +150,7 @@ ArmEnableDataCache dsb isb bx LR - + ArmDisableDataCache ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) @@ -168,7 +168,7 @@ ArmEnableInstructionCache dsb isb bx LR - + ArmDisableInstructionCache ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) @@ -223,14 +223,14 @@ ArmV7AllDataCachesOperation beq Finished mov R10, #0 -Loop1 +Loop1 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level and R12, R12, #7 ; get those 3 bits alone cmp R12, #2 blt Skip ; no cache or only instruction cache at this level mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction - isb ; isb to sync the change to the CacheSizeID reg + isb ; isb to sync the change to the CacheSizeID reg mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR) and R2, R12, #&7 ; extract the line length field add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes) @@ -240,10 +240,10 @@ Loop1 ldr R7, =0x00007FFF ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned) -Loop2 +Loop2 mov R9, R4 ; R9 working copy of the max way size (right aligned) -Loop3 +Loop3 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11 orr R0, R0, R7, LSL R2 ; factor in the index number @@ -253,11 +253,11 @@ Loop3 bge Loop3 subs R7, R7, #1 ; decrement the index bge Loop2 -Skip +Skip add R10, R10, #2 ; increment the cache number cmp R3, R10 bgt Loop1 - + Finished dsb ldmfd SP!, {r4-r12, lr} @@ -272,14 +272,14 @@ ArmV7PerformPoUDataCacheOperation beq Finished2 mov R10, #0 -Loop4 +Loop4 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level and R12, R12, #7 ; get those 3 bits alone cmp R12, #2 blt Skip2 ; no cache or only instruction cache at this level mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction - isb ; isb to sync the change to the CacheSizeID reg + isb ; isb to sync the change to the CacheSizeID reg mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR) and R2, R12, #&7 ; extract the line length field add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes) @@ -289,10 +289,10 @@ Loop4 ldr R7, =0x00007FFF ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned) -Loop5 +Loop5 mov R9, R4 ; R9 working copy of the max way size (right aligned) -Loop6 +Loop6 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11 orr R0, R0, R7, LSL R2 ; factor in the index number @@ -302,11 +302,11 @@ Loop6 bge Loop6 subs R7, R7, #1 ; decrement the index bge Loop5 -Skip2 +Skip2 add R10, R10, #2 ; increment the cache number cmp R3, R10 bgt Loop4 - + Finished2 dsb ldmfd SP!, {r4-r12, lr} @@ -315,12 +315,12 @@ Finished2 ArmDataMemoryBarrier dmb bx LR - + ArmDataSyncronizationBarrier ArmDrainWriteBuffer dsb bx LR - + ArmInstructionSynchronizationBarrier isb bx LR @@ -332,7 +332,7 @@ ArmReadVBar ArmWriteVBar // Set the Address of the Vector Table in the VBAR register - mcr p15, 0, r0, c12, c0, 0 + mcr p15, 0, r0, c12, c0, 0 // Ensure the SCTLR.V bit is clear mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) bic r0, r0, #0x00002000 ; clear V bit