X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPkg%2FLibrary%2FArmMmuLib%2FAArch64%2FArmMmuLibCore.c;h=d66df3e17a02a17c71b4ff947963de3f584320a6;hp=84a689af7c8aef4f969d1a27c0084f6dfc5e9631;hb=76c23f9e0d0d65866e4195b0bc12c1ca2763ced2;hpb=e93cb72e597df7b37aad7910787b8ecaeac31382 diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 84a689af7c..d66df3e17a 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -3,6 +3,7 @@ * * Copyright (c) 2011-2014, ARM Limited. All rights reserved. * Copyright (c) 2016, Linaro Limited. All rights reserved. +* Copyright (c) 2017, Intel Corporation. All rights reserved.
* * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -34,6 +35,10 @@ ArmMemoryAttributeToPageAttribute ( ) { switch (Attributes) { + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE: + case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE: + return TT_ATTR_INDX_MEMORY_WRITE_BACK; + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; @@ -89,7 +94,7 @@ PageAttributeToGcdAttribute ( // Determine protection attributes if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) { // Read only cases map to write-protect - GcdAttributes |= EFI_MEMORY_WP; + GcdAttributes |= EFI_MEMORY_RO; } // Process eXecute Never attribute @@ -100,27 +105,6 @@ PageAttributeToGcdAttribute ( return GcdAttributes; } -ARM_MEMORY_REGION_ATTRIBUTES -GcdAttributeToArmAttribute ( - IN UINT64 GcdAttributes - ) -{ - switch (GcdAttributes & 0xFF) { - case EFI_MEMORY_UC: - return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; - case EFI_MEMORY_WC: - return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; - case EFI_MEMORY_WT: - return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH; - case EFI_MEMORY_WB: - return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; - default: - DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes)); - ASSERT (0); - return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; - } -} - #define MIN_T0SZ 16 #define BITS_PER_LEVEL 9 @@ -298,7 +282,7 @@ GetBlockEntryListFromAddress ( } // Create a new translation table - TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE); + TranslationTable = AllocatePages (1); if (TranslationTable == NULL) { return NULL; } @@ -321,7 +305,7 @@ GetBlockEntryListFromAddress ( // // Create a new translation table - TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE); + TranslationTable = AllocatePages (1); if (TranslationTable == NULL) { return NULL; } @@ -349,7 +333,7 @@ GetBlockEntryListFromAddress ( } STATIC -RETURN_STATUS +EFI_STATUS UpdateRegionMapping ( IN UINT64 *RootTable, IN UINT64 RegionStart, @@ -367,7 +351,7 @@ UpdateRegionMapping ( // Ensure the Length is aligned on 4KB boundary if ((RegionLength == 0) || ((RegionLength & (SIZE_4KB - 1)) != 0)) { ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); - return RETURN_INVALID_PARAMETER; + return EFI_INVALID_PARAMETER; } do { @@ -377,7 +361,7 @@ UpdateRegionMapping ( BlockEntry = GetBlockEntryListFromAddress (RootTable, RegionStart, &TableLevel, &BlockEntrySize, &LastBlockEntry); if (BlockEntry == NULL) { // GetBlockEntryListFromAddress() return NULL when it fails to allocate new pages from the Translation Tables - return RETURN_OUT_OF_RESOURCES; + return EFI_OUT_OF_RESOURCES; } if (TableLevel != 3) { @@ -398,18 +382,18 @@ UpdateRegionMapping ( // Break the inner loop when next block is a table // Rerun GetBlockEntryListFromAddress to avoid page table memory leak - if (TableLevel != 3 && + if (TableLevel != 3 && BlockEntry <= LastBlockEntry && (*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) { break; } } while ((RegionLength >= BlockEntrySize) && (BlockEntry <= LastBlockEntry)); } while (RegionLength != 0); - return RETURN_SUCCESS; + return EFI_SUCCESS; } STATIC -RETURN_STATUS +EFI_STATUS FillTranslationTable ( IN UINT64 *RootTable, IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion @@ -424,38 +408,93 @@ FillTranslationTable ( ); } -RETURN_STATUS -SetMemoryAttributes ( +STATIC +UINT64 +GcdAttributeToPageAttribute ( + IN UINT64 GcdAttributes + ) +{ + UINT64 PageAttributes; + + switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) { + case EFI_MEMORY_UC: + PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY; + break; + case EFI_MEMORY_WC: + PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE; + break; + case EFI_MEMORY_WT: + PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE; + break; + case EFI_MEMORY_WB: + PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; + break; + default: + PageAttributes = TT_ATTR_INDX_MASK; + break; + } + + if ((GcdAttributes & EFI_MEMORY_XP) != 0 || + (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC) { + if (ArmReadCurrentEL () == AARCH64_EL2) { + PageAttributes |= TT_XN_MASK; + } else { + PageAttributes |= TT_UXN_MASK | TT_PXN_MASK; + } + } + + if ((GcdAttributes & EFI_MEMORY_RO) != 0) { + PageAttributes |= TT_AP_RO_RO; + } + + return PageAttributes | TT_AF; +} + +EFI_STATUS +ArmSetMemoryAttributes ( IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, - IN UINT64 Attributes, - IN EFI_PHYSICAL_ADDRESS VirtualMask + IN UINT64 Attributes ) { - RETURN_STATUS Status; - ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion; + EFI_STATUS Status; UINT64 *TranslationTable; - - MemoryRegion.PhysicalBase = BaseAddress; - MemoryRegion.VirtualBase = BaseAddress; - MemoryRegion.Length = Length; - MemoryRegion.Attributes = GcdAttributeToArmAttribute (Attributes); + UINT64 PageAttributes; + UINT64 PageAttributeMask; + + PageAttributes = GcdAttributeToPageAttribute (Attributes); + PageAttributeMask = 0; + + if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) { + // + // No memory type was set in Attributes, so we are going to update the + // permissions only. + // + PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK; + PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK | + TT_PXN_MASK | TT_XN_MASK); + } TranslationTable = ArmGetTTBR0BaseAddress (); - Status = FillTranslationTable (TranslationTable, &MemoryRegion); - if (RETURN_ERROR (Status)) { + Status = UpdateRegionMapping ( + TranslationTable, + BaseAddress, + Length, + PageAttributes, + PageAttributeMask); + if (EFI_ERROR (Status)) { return Status; } // Invalidate all TLB entries so changes are synced ArmInvalidateTlb (); - return RETURN_SUCCESS; + return EFI_SUCCESS; } STATIC -RETURN_STATUS +EFI_STATUS SetMemoryRegionAttribute ( IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, @@ -463,23 +502,23 @@ SetMemoryRegionAttribute ( IN UINT64 BlockEntryMask ) { - RETURN_STATUS Status; + EFI_STATUS Status; UINT64 *RootTable; RootTable = ArmGetTTBR0BaseAddress (); Status = UpdateRegionMapping (RootTable, BaseAddress, Length, Attributes, BlockEntryMask); - if (RETURN_ERROR (Status)) { + if (EFI_ERROR (Status)) { return Status; } // Invalidate all TLB entries so changes are synced ArmInvalidateTlb (); - return RETURN_SUCCESS; + return EFI_SUCCESS; } -RETURN_STATUS +EFI_STATUS ArmSetMemoryRegionNoExec ( IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length @@ -500,7 +539,7 @@ ArmSetMemoryRegionNoExec ( ~TT_ADDRESS_MASK_BLOCK_ENTRY); } -RETURN_STATUS +EFI_STATUS ArmClearMemoryRegionNoExec ( IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length @@ -518,7 +557,7 @@ ArmClearMemoryRegionNoExec ( Mask); } -RETURN_STATUS +EFI_STATUS ArmSetMemoryRegionReadOnly ( IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length @@ -531,7 +570,7 @@ ArmSetMemoryRegionReadOnly ( ~TT_ADDRESS_MASK_BLOCK_ENTRY); } -RETURN_STATUS +EFI_STATUS ArmClearMemoryRegionReadOnly ( IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length @@ -544,7 +583,7 @@ ArmClearMemoryRegionReadOnly ( ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK)); } -RETURN_STATUS +EFI_STATUS EFIAPI ArmConfigureMmu ( IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, @@ -553,31 +592,27 @@ ArmConfigureMmu ( ) { VOID* TranslationTable; - UINTN TranslationTablePageCount; UINT32 TranslationTableAttribute; - ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry; UINT64 MaxAddress; - UINT64 TopAddress; UINTN T0SZ; UINTN RootTableEntryCount; UINT64 TCR; - RETURN_STATUS Status; + EFI_STATUS Status; if(MemoryTable == NULL) { ASSERT (MemoryTable != NULL); - return RETURN_INVALID_PARAMETER; + return EFI_INVALID_PARAMETER; } - // Identify the highest address of the memory table - MaxAddress = MemoryTable->PhysicalBase + MemoryTable->Length - 1; - MemoryTableEntry = MemoryTable; - while (MemoryTableEntry->Length != 0) { - TopAddress = MemoryTableEntry->PhysicalBase + MemoryTableEntry->Length - 1; - if (TopAddress > MaxAddress) { - MaxAddress = TopAddress; - } - MemoryTableEntry++; - } + // + // Limit the virtual address space to what we can actually use: UEFI + // mandates a 1:1 mapping, so no point in making the virtual address + // space larger than the physical address space. We also have to take + // into account the architectural limitations that result from UEFI's + // use of 4 KB pages. + // + MaxAddress = MIN (LShiftU64 (1ULL, ArmGetPhysicalAddressBits ()) - 1, + MAX_ALLOC_ADDRESS); // Lookup the Table Level to get the information LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount); @@ -607,7 +642,7 @@ ArmConfigureMmu ( } else { DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress)); ASSERT (0); // Bigger than 48-bit memory space are not supported - return RETURN_UNSUPPORTED; + return EFI_UNSUPPORTED; } } else if (ArmReadCurrentEL () == AARCH64_EL1) { // Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1. @@ -629,21 +664,33 @@ ArmConfigureMmu ( } else { DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress)); ASSERT (0); // Bigger than 48-bit memory space are not supported - return RETURN_UNSUPPORTED; + return EFI_UNSUPPORTED; } } else { ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3. - return RETURN_UNSUPPORTED; + return EFI_UNSUPPORTED; } + // + // Translation table walks are always cache coherent on ARMv8-A, so cache + // maintenance on page tables is never needed. Since there is a risk of + // loss of coherency when using mismatched attributes, and given that memory + // is mapped cacheable except for extraordinary cases (such as non-coherent + // DMA), have the page table walker perform cached accesses as well, and + // assert below that that matches the attributes we use for CPU accesses to + // the region. + // + TCR |= TCR_SH_INNER_SHAREABLE | + TCR_RGN_OUTER_WRITE_BACK_ALLOC | + TCR_RGN_INNER_WRITE_BACK_ALLOC; + // Set TCR ArmSetTCR (TCR); // Allocate pages for translation table - TranslationTablePageCount = EFI_SIZE_TO_PAGES(RootTableEntryCount * sizeof(UINT64)); - TranslationTable = (UINT64*)AllocateAlignedPages (TranslationTablePageCount, TT_ALIGNMENT_DESCRIPTION_TABLE); + TranslationTable = AllocatePages (1); if (TranslationTable == NULL) { - return RETURN_OUT_OF_RESOURCES; + return EFI_OUT_OF_RESOURCES; } // We set TTBR0 just after allocating the table to retrieve its location from the subsequent // functions without needing to pass this value across the functions. The MMU is only enabled @@ -671,39 +718,25 @@ ArmConfigureMmu ( TranslationTableAttribute = TT_ATTR_INDX_INVALID; while (MemoryTable->Length != 0) { - // Find the memory attribute for the Translation Table - if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) && - ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) { - TranslationTableAttribute = MemoryTable->Attributes; - } + + DEBUG_CODE_BEGIN (); + // Find the memory attribute for the Translation Table + if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase && + (UINTN)TranslationTable + EFI_PAGE_SIZE <= MemoryTable->PhysicalBase + + MemoryTable->Length) { + TranslationTableAttribute = MemoryTable->Attributes; + } + DEBUG_CODE_END (); Status = FillTranslationTable (TranslationTable, MemoryTable); - if (RETURN_ERROR (Status)) { + if (EFI_ERROR (Status)) { goto FREE_TRANSLATION_TABLE; } MemoryTable++; } - // Translate the Memory Attributes into Translation Table Register Attributes - if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) || - (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) { - TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_NON_CACHEABLE | TCR_RGN_INNER_NON_CACHEABLE; - } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || - (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) { - TCR |= TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WRITE_BACK_ALLOC | TCR_RGN_INNER_WRITE_BACK_ALLOC; - } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) || - (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) { - TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_WRITE_THROUGH | TCR_RGN_INNER_WRITE_THROUGH; - } else { - // If we failed to find a mapping that contains the root translation table then it probably means the translation table - // is not mapped in the given memory map. - ASSERT (0); - Status = RETURN_UNSUPPORTED; - goto FREE_TRANSLATION_TABLE; - } - - // Set again TCR after getting the Translation Table attributes - ArmSetTCR (TCR); + ASSERT (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK || + TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK); ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) | // mapped to EFI_MEMORY_UC MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC @@ -711,14 +744,15 @@ ArmConfigureMmu ( MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)); // mapped to EFI_MEMORY_WB ArmDisableAlignmentCheck (); + ArmEnableStackAlignmentCheck (); ArmEnableInstructionCache (); ArmEnableDataCache (); ArmEnableMmu (); - return RETURN_SUCCESS; + return EFI_SUCCESS; FREE_TRANSLATION_TABLE: - FreePages (TranslationTable, TranslationTablePageCount); + FreePages (TranslationTable, 1); return Status; }