X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPlatformPkg%2FArmPlatformPkg.dec;h=4100b15e516c8568af9cc1ccd0b8a0b7edce35ac;hp=1a7a30efadb53c0b8747eda4aa86c5723cfe0143;hb=db1b9ea0b4e9bb13a0f8232f1e3047aad5b878b7;hpb=d0da41c285bf0b7abf5c82b9a0563d3bb545fc95 diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 1a7a30efad..4100b15e51 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -1,21 +1,21 @@ #/** @file # -# Copyright (c) 2011, ARM Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. # -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. # #**/ [Defines] DEC_SPECIFICATION = 0x00010005 PACKAGE_NAME = ArmPlatformPkg - PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b + PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b PACKAGE_VERSION = 0.1 ################################################################################ @@ -36,10 +36,16 @@ # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf # gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } } + # + # Following Guid must match FILE_GUID in SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableRuntimeDxe.inf + # + gVariableAuthenticatedRuntimeDxeFileGuid = { 0x2226f30f, 0x3d5b, 0x402d, {0x99, 0x36, 0xa9, 0x71, 0x84, 0xEB, 0x45, 0x16 } } ## Include/Guid/ArmGlobalVariableHob.h gArmGlobalVariableGuid = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} } + gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } } + [Ppis] ## Include/Ppi/ArmGlobalVariable.h gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} } @@ -47,28 +53,31 @@ [PcdsFeatureFlag.common] # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0. gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012 - + gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001 gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002 gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004 + gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C + + # Disable the GOP controller on ExitBootServices(). By default the value is FALSE, + # we assume the OS will handle the FrameBuffer from the UEFI GOP information. + gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D + [PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039 gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038 - + # Stack for CPU Cores in Secure Mode gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006 - # Stack for CPU Cores in Secure Monitor Mode - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008 - # Stack for CPU Cores in Non Secure Mode - gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT32|0x00000009 + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A - + # Size of the region used by UEFI in permanent memory (Reserved 128MB by default) gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015 @@ -76,13 +85,16 @@ # = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */ gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016 # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list - # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped. + # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped. gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017 gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018 # Size to reserve in the primary core stack for SEC Global Variables gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031 + # Boot Monitor FileSystem + gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A + # # ARM Primecells # @@ -99,20 +111,17 @@ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021 ## PL011 UART - gArmPlatformTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0x00000000|UINT32|0x0000001F - gArmPlatformTokenSpaceGuid.PcdUartDefaultTimeout|0x00000000|UINT32|0x00000020 - - ## PL031 RealTimeClock - gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 - gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022 + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F + gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020 + gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D ## PL061 GPIO gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025 - - ## PL111 Lcd + + ## PL111 Lcd & HdLcd gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027 - + ## PL180 MCI gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028 gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029 @@ -124,18 +133,92 @@ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E - gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""|VOID*|0x000000F - # PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath: + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F + # PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath: # - 0 = an EFI application # - 1 = a Linux kernel with ATAG support # - 2 = a Linux kernel with FDT support gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010 - gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L""|VOID*|0x00000011 - - ## Timeout value for displaying progressing bar in before boot OS. - # According to UEFI 2.0 spec, the default TimeOut should be 0xffff. - gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|0xffff|UINT16|0x0000001A - + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C - + +[PcdsFixedAtBuild.common,PcdsDynamic.common] + ## PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 + gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022 + + # + # Inclusive range of allowed PCI buses. + # + gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E + gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F + + # + # Bases, sizes and translation offsets of IO and MMIO spaces, respectively. + # Note that "IO" is just another MMIO range that simulates IO space; there + # are no special instructions to access it. + # + # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are + # specific to their containing address spaces. In order to get the physical + # address for the CPU, for a given access, the respective translation value + # has to be added. + # + # The translations always have to be initialized like this, using UINT64: + # + # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space + # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space + # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space + # + # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase; + # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base; + # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base; + # + # because (a) the target address space (ie. the cpu-physical space) is + # 64-bit, and (b) the translation values are meant as offsets for *modular* + # arithmetic. + # + # Accordingly, the translation itself needs to be implemented as: + # + # UINT64 UntranslatedIoAddress; // input parameter + # UINT32 UntranslatedMmio32Address; // input parameter + # UINT64 UntranslatedMmio64Address; // input parameter + # + # UINT64 TranslatedIoAddress; // output parameter + # UINT64 TranslatedMmio32Address; // output parameter + # UINT64 TranslatedMmio64Address; // output parameter + # + # TranslatedIoAddress = UntranslatedIoAddress + + # PcdPciIoTranslation; + # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address + + # PcdPciMmio32Translation; + # TranslatedMmio64Address = UntranslatedMmio64Address + + # PcdPciMmio64Translation; + # + # The modular arithmetic performed in UINT64 ensures that the translation + # works correctly regardless of the relation between IoCpuBase and + # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and + # PcdPciMmio64Base. + # + gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040 + gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041 + gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042 + gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043 + gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044 + gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045 + gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046 + gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047 + gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048 + +[PcdsFixedAtBuild.ARM] + # Stack for CPU Cores in Secure Monitor Mode + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008 + +[PcdsFixedAtBuild.AARCH64] + # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64. + # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize + # and PcdCPUCoreSecSecondaryStackSize + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008 +