X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPlatformPkg%2FArmVExpressPkg%2FLibrary%2FArmVExpressLibCTA9x4%2FCTA9x4.c;h=b314f51b01ac87a6f8f1d4eb3c5b29b54cb4c4b4;hp=8415842fb597e5a6c10217d23ee0f9b4c11b3247;hb=0db25ccc6cf1d05dc6b8fd9b07d033b40c387c88;hpb=bf276b45b8613a7b84d8ad7a68182863364cca0a diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c index 8415842fb5..b314f51b01 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -13,7 +13,6 @@ **/ #include -#include #include #include #include @@ -23,20 +22,65 @@ #include #include -#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1); +#include + +#include + +#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1); + +ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4[] = { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 1 + 0x0, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 2 + 0x0, 0x2, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 3 + 0x0, 0x3, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + } +}; // DDR2 timings PL341_DMC_CONFIG DDRTimings = { - .base = ARM_VE_DMC_BASE, - .phy_ctrl_base = 0x0, //There is no DDR2 PHY controller on CTA9 test chip .MaxChip = 1, .IsUserCfg = TRUE, .User0Cfg = 0x7C924924, .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT), .HasQos = TRUE, - .refresh_prd = 0x3D0, - .cas_latency = 0x8, - .write_latency = 0x3, + .RefreshPeriod = 0x3D0, + .CasLatency = 0x8, + .WriteLatency = 0x3, .t_mrd = 0x2, .t_ras = 0xA, .t_rc = 0xE, @@ -60,25 +104,6 @@ PL341_DMC_CONFIG DDRTimings = { .ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK), }; -/** - Return if Trustzone is supported by your platform - - A non-zero value must be returned if you want to support a Secure World on your platform. - ArmVExpressTrustzoneInit() will later set up the secure regions. - This function can return 0 even if Trustzone is supported by your processor. In this case, - the platform will continue to run in Secure World. - - @return A non-zero value if Trustzone supported. - -**/ -UINTN -ArmPlatformTrustzoneSupported ( - VOID - ) -{ - return (MmioRead32(ARM_VE_SYS_CFGRW1_REG) & ARM_VE_CFGRW1_TZASC_EN_BIT_MASK); -} - /** Return the current Boot Mode @@ -92,36 +117,17 @@ ArmPlatformGetBootMode ( VOID ) { - return BOOT_WITH_FULL_CONFIGURATION; -} - -/** - Remap the memory at 0x0 - - Some platform requires or gives the ability to remap the memory at the address 0x0. - This function can do nothing if this feature is not relevant to your platform. - -**/ -VOID -ArmPlatformBootRemapping ( - VOID - ) -{ - UINT32 Value; - - if (FeaturePcdGet(PcdNorFlashRemapping)) { - SerialPrint ("Secure ROM at 0x0\n\r"); + if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) { + return BOOT_WITH_FULL_CONFIGURATION; } else { - Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1 - // Remap the DRAM to 0x0 - MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM); + return BOOT_ON_S2_RESUME; } } /** Initialize controllers that must setup in the normal world - This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei in the PEI phase. **/ @@ -151,6 +157,52 @@ ArmPlatformInitializeSystemMemory ( VOID ) { - PL341DmcInit(&DDRTimings); + UINT32 Value; + + // Memory Map remapping + if (FeaturePcdGet(PcdNorFlashRemapping)) { + SerialPrint ("Secure ROM at 0x0\n\r"); + } else { + Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1 + // Remap the DRAM to 0x0 + MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM); + } + + PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings); PL301AxiInit(ARM_VE_FAXI_BASE); } + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = sizeof(mVersatileExpressMpCoreInfoCTA9x4) / sizeof(ARM_CORE_INFO); + *ArmCoreTable = mVersatileExpressMpCoreInfoCTA9x4; + + return EFI_SUCCESS; +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof(gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} +